s71gl128nc0 Meet Spansion Inc., s71gl128nc0 Datasheet - Page 105

• Manufacturer Part Number: s71gl128nc0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 64 Megabit 4m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Functional Description
Legend:L = V
Notes:
1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
3. Can be either V
Power Down (for 32M, 64M Only)
November 2, 2004 pSRAM_Type07_13_A1
Standby (Deselect)
Output Disable (Note 1)
Output Disable (No Read)
Read (Upper Byte)
Read (Lower Byte)
Read (Word)
No Write
Write (Upper Byte)
Write (Lower Byte)
Write (Word)
Power Down
Sleep (default)
1ms limitation.
selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for
details.
4M Partial
8M Partial
Mode
Power Down
Mode
IL
, H = V
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the
device in power-down mode and maintains the low-power idle state as long as
CE2 is kept Low. CE2 High resumes the device from power-down mode. These
devices have three power-down modes. These can be programmed by series of
read/write operation. Each mode has following features.
The default state is Sleep and it is the lowest power consumption but all data is
lost once CE2 is brought to Low for Power Down. It is not required to program to
Sleep mode after power-up.
IL
or V
Retention Data
IH
4M bit
8M bit
IH
No
but must be valid before Read or Write.
, X can be either V
32M
A d v a n c e
CE2#
H
H
L
CE1#
00000h to 3FFFFh
00000h to 7FFFFh
Retention Address
H
L
X
N/A
WE#
i n f o r m a t i o n
IL
X
H
H
X
L
or V
pSRAM Type 7
IH
OE#
, High-Z = High Impedance.
X
H
H
X
L
Sleep (default)
16M Partial
LB#
8M Partial
X
H
H
H
H
X
L
L
L
L
X
Mode
UB#
H
H
X
X
H
H
X
L
L
L
L
Retention Data
Note 3
A
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
16M bit
8M bit
21-0
X
X
No
64M
Output Valid
Output Valid
Input Valid
Input Valid
High-Z
High-Z
High-Z
High-Z
Invalid
Invalid
High-Z
DQ
8-1
00000h to 7FFFFh
00000h to FFFFFh
Retention Address
N/A
Output Valid
Output Valid
Input Valid
Input Valid
DQ
High-Z
High-Z
High-Z
High-Z
Invalid
Invalid
High-Z
16-9
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