s71gl128nc0 Meet Spansion Inc., s71gl128nc0 Datasheet - Page 24

• Manufacturer Part Number: s71gl128nc0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 64 Megabit 4m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Device Bus Operations
Legend: L = Logic Low = V
Address, A
Notes:
1. Addresses are AMax:A0 in word mode. Sector addresses are A
2. If WP# = V
3. D
24
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are
unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending
on version ordered.)
Figure
IN
or D
VersatileIO
Requirements for Reading Array Data
Operation
5).
IN
OUT
= Address In, D
IL
as required by command sequence, data polling, or sector protect algorithm (see
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device.
require, and the resulting output. The following subsections describe each of
these operations in further detail.
The VersatileIO
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
device.
For example, a V
driving and receiving signals to and from other 1.8-V or 3-V devices on the same
data bus.
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
, the first or last sector group remains protected. If WP# = V
TM
Table 1
IL
IL
(V
. CE# is the power control and selects the device. OE# is the output
, H = Logic High = V
IN
V
CC
IO
= Data In, D
lists the device bus operations, the inputs and control levels they
CE#
±
) Control
X
TM
L
L
L
L
I/O
0.3 V
(V
of 1.65 V to 3.6 V allows for I/O at the 1.8 or 3 volt levels,
IO
Table 1. Device Bus Operations
) control allows the host system to set the voltage levels
S29GLxxxN MirrorBit
OUT
OE#
IO
A d v a n c e
H
H
H
X
X
L
. See Ordering Information for V
IH
= Data Out
, V
ID
WE#
= 11.5–12.5 V, V
H
H
L
L
X
X
TM
Flash Family
I n f o r m a t i o n
RESET#
Max
V
0.3 V
CC
H
H
H
H
L
:A16 in both modes.
±
HH
= 11.5–12.5V, X = Don’t Care, SA = Sector
WP#/
Note 2
ACC
V
X
H
X
X
HH
IH
IO
, the first or last sector will be
options on this
Addresses
(Note 1)
S29GLxxxN_MCP_A1 December 15, 2004
A
A
A
X
X
X
IN
IN
IN
IH
Figure
.
2,
DQ0–DQ15
(Note 3)
(Note 3)
Figure
High-Z
High-Z
High-Z
D
OUT
4, and