s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 111

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
August 30, 2004 pSRAM_Type01_12_A1
CE#
Dat a Out
WE#
Page A ddr es s
Wor d A ddr es s
(A0 - A3 )
LB#, UB#
Partial Array Self Refresh (PAR)
(A4 - A 20)
There are several power savings modes.
T P artial Array Self Refresh
T T emperature Compensated Refresh (64M)
T Deep Sleep Mode
T Reduced Memory Size (32M, 16M)
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 39 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure xxx.
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register set-
tings for the PASR operation are defined in T able xxx. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = V
A d v a n c e
High-Z
t
AS
t
WC
t
LBW,
t
WP
t
I n f o r m a t i o n
CW
t
UBW
t
DW
pSRAM Type 1
t
DH
t
PGMAX
t
PWC
t
PDW
t
PDH
t
PDW
IH
)
t
PDH
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