emc2105 Standard Microsystems Corp., emc2105 Datasheet - Page 70

• Manufacturer Part Number: emc2105
• Description: Emc2105 Rpm-based High Side Fan Controller With Hardware Thermal Shutdown
• Manufacturer: Standard Microsystems Corp.

ADDR
E0h
ADDR
ADDR
E1h
E2
Revision 1.74 (05-08-08)
6.31
6.32
6.33
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER
Muxed Pin
The Muxed Pin Configuration Register controls the pin function for the multiple function GPIO pin.
Bit 0 - GPIO1_CFG - Determines the pin function for the CLK_IN / GPIO1 pin.
The GPIO Direction Register 1 controls the direction of GPIOs 1 through 6. When muxable pins are
not configured as a GPIO ports the respective bits are ignored.
Bit 5 - 0 - GPIOx_DIR - Controls the input / output state of GPIOs. The bit is not used if the pin is not
configured as a GPIO.
The GPIO Output Configuration Register controls the output pin type of the GPIO pin. Bit 0 -
GPIO1_OT - Determines the output type for GPIOx.
Muxed Pin Configuration Register
GPIO Direction Register
GPIO Pin Output Configuration Register
Config
‘0’ - The CLK_IN / GPIO1 pin functions as a clock input for the RPM based Fan Speed Control
Algorithm (FSC).
‘1’ (default) - The CLK_IN / GPIO1 pin functions as a GPIO.
‘0’ (default) - The GPIO is configured as an input.
‘1’ - The GPIO is configured as an output.
‘0’ (default) - GPIO1 is configured as an open drain output (if enabled as an output).
‘1’ - GPIO1is configured as a push-pull output (if enabled as an output).
REGISTER
REGISTER
Direction 1
Output
Config
GPIO
GPIO
B7
Table 6.49 GPIO Pin Output Configuration Register
-
Table 6.47 Muxed Pin Configuration Register
B7
B7
-
-
Table 6.48 GPIO Direction Register
B6
-
B6
B6
-
-
DATASHEET
B5
RPM-Based High Side Fan Controller with Hardware Thermal Shutdown
-
B5
B5
-
-
70
B4
B4
B4
-
-
-
B3
B3
-
-
B3
-
B2
B2
-
-
B2
-
B1
B1
-
-
B1
-
1_DIR
GPIO
1_OT
GPIO
B0
B0
SMSC EMC2105
GPIO1
_CFG
B0
Datasheet
DEFAULT
DEFAULT
00h
00h
DEFAULT
01h