emc2106 Standard Microsystems Corp., emc2106 Datasheet - Page 59

• Manufacturer Part Number: emc2106
• Description: Emc2106 Dual Rpm-based Linear Fan Controller With Hardware Thermal Shutdown
• Manufacturer: Standard Microsystems Corp.

ADDR
20h
ADDR
1Ch
1Dh
1Ah
1Bh
19h
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
Datasheet
SMSC EMC2106
6.8
6.9
R/W
R/W
once
once
once
once
once
R/W
R/W
R/W
R/W
R/W
R/W
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown
circuitry.
Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the
appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will
be set.
The Configuration Register controls the basic functionality of the EMC2106. The bits are described
below. The Configuration Register is software locked.
Bit 7 - MASK - Blocks the ALERT# pin from being asserted.
Bit 4 - SYS4 - Enables the high temperature limit for the External Diode 4 channel to trigger the Critical
/ Thermal Shutdown circuitry (see
to measure a voltage input. In this case, the External Diode 4 channel is disabled and not compared
against any limits.
Critical Temperature Limit Registers
Configuration Register
Configuration
REGISTER
‘0’ (default) - The ALERT# pin is unmasked. If any bit in either status register is set, the ALERT#
pins will be asserted (unless individually masked via the Mask Register)
‘1’ - The ALERT# pin is masked and will not be asserted.
‘0’ (default) - the External Diode 4 channel high limit will not be linked to the SYS_SHDN# pin. If
the temperature exceeds the limit, the ALERT# pin will be asserted normally.
‘1’ - the External Diode 4 channel high limit will be linked to the SYS_SHDN# pin. If the temperature
exceeds the limit then the SYS_SHDN# pin will be asserted. The SYS_SHDN# pin will be released
External Diode
External Diode
External Diode
External Diode
Internal Diode
1 Tcrit Limit
2 Tcrit Limit
3 Tcrit Limit
4 Tcrit Limit
REGISTER
Tcrit Limit
MASK
B7
Sign
Sign
Sign
Sign
Sign
B7
Table 6.12 Configuration Register
B6
Table 6.11 Limit Registers
-
B6
Section
64
64
64
64
64
DATASHEET
B5
-
6.1). This bit is ignored if the DP3 / DN3 pins are configured
59
B5
32
32
32
32
32
SYS4
B4
B4
16
16
16
16
16
SYS3
B3
B3
8
8
8
8
8
SYS2
B2
B2
4
4
4
4
4
SYS1
B1
B1
2
2
2
2
2
Revision 1.74 (05-08-08)
B0
APD
1
1
1
1
1
B0
DEFAULT
(+100°C)
(+100°C)
(+100°C)
(+100°C)
(+100°C)
DEFAULT
64h
64h
64h
64h
64h
00h