hi-8599 Holt Integrated Circuits, Inc., hi-8599 Datasheet
hi-8599
Related parts for hi-8599
hi-8599 Summary of contents
Page 1
... CLK, by either 10 or 80. The master clock is used to set the timing of the ARINC transmission within the required resolution. The HI-8599 is nearly identical to the HI-8589 but has a TEST input pin not found in the HI-8589. APPLICATIONS ! ...
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... INPUT CWSTR INPUT CLK INPUT TX CLK OUTPUT MR INPUT TEST INPUT HI-8599 DESCRIPTION +5V ±5% +9.5V to +10.5V -9.5V to -10.5V ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag Receiver 2 data ready flag Receiver data byte selection (0 = BYTE BYTE 2) ...
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... FUNCTIONAL DESCRIPTION (cont.) CONTROL WORD REGISTER The HI-8599 contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to Each flip flop provides options to the user as follows: DATA BUS FUNCTION CONTROL PIN If enabled, the transmitter’s digital BDO5 ...
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... ONES SHIFT REGISTER NULL SHIFT REGISTER SHIFT REGISTER ZEROS HI-8599 bit rate is checked. With exactly 1 MHz input clock frequency, the acceptable data bit rates are as follows: DATA BIT RATE MIN DATA BIT RATE MAX LOW SPEED 4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a 12K -14 ...
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... LOAD SHIFT REGISTER FIFO DATA BUS FIGURE 3. HI-8599 TRANSMITTER PARITY The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. ...
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... FUNCTIONAL DESCRIPTION (cont.) LINE DRIVER OPERATION The line driver in the HI-8599 is designed to directly drive the ARINC 429 bus. The two ARINC outputs (TXA(OUT) and TXB(OUT)) provide a differential voltage to produce a +10 volt One, a -10 volt Zero, and a 0 volt Null. Setting Control Register bit zero causes a slope of 1 ...
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... BYTE SELECT SEL ENABLE BYTE ON BUS EN DATA BUS DATA BUS PL1 PL2 TX/R PL2 t PL2EN TX/R ENTX t ENDAT TXA(OUT) TXB(OUT) V DIFF (TXA(OUT) - TXB(OUT)) 10% one level HI-8599 RECEIVER OPERATON t D/R DON'T CARE t SELEN t ENSEL t D/REN BYTE 1 VALID t ENDATA TRANSMITTER OPERATION BYTE 1 VALID t DWSET t DWHLD ...
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... TIMING DIAGRAMS (cont.) BIT 32 429DI D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX TXA(OUT) TXB(OUT) HI-8599 REPEATER OPERATION TIMING t END ENEN EN t ENSEL t SELEN t PLEN t t PLEN ENPL t TX/REN HOLT INTEGRATED CIRCUITS 8 DON'T CARE t ENSEL t TX/R t ENTX/R ...
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... BI-DIRECTIONAL INPUTS Input Voltage: Input Current: Pull-down Current (TEST Pin) OTHER INPUTS Input Voltage: Input Current: HI-8599 Power Dissipation at 25°C -0.3V to +7V +12.5V Plastic PLCC/PQFP Ceramic J-LEAD CERQUAD -12.5V DC Current Drain per pin -29V to +29V -0 ...
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... Logic "1" Output Voltage Logic "0" Output Voltage Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: Operating Voltage Range Operating Supply Current HI-8599 CONDITIONS SYMBOL V no load and magnitude at pin DOUT V NOUT " " " I OUT ...
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... Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Line driver transition differential times: (High Speed) (Low Speed) REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH MASTER RESET PULSE WIDTH ARINC DATA RATE AND BIT TIMING HI-8599 SYMBOL Pulse Width - CWSTR t CWSTR CWSTR HIGH ...
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... ADDITIONAL HI-8599 PIN CONFIGURATIONS (See page 1 for the 44-Pin Plastic Quad Flat Pack (PQFP) pin configuration) 429DI2(B) 7 D/R1 8 D/R2 9 SEL 10 EN1 11 EN2 12 BD15 13 BD14 14 BD13 15 BD12 16 BD11 17 HI-8599PJI HI-8599PJT 44-Pin Plastic J-Lead PLCC ORDERING INFORMATION HI - 8599 PART NUMBER No dash number ...
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... SQ. .039 ±.005 (.990 ±.127) .019 ±.002 (.483 ± .051) HI-8599 PACKAGE DIMENSIONS PIN NO. 1 IDENT .045 x 45° .653 ±.004 (16.586 ±.102) SQ. See Detail A .610 ±.020 (15.494±.508) .688 ± ...
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... PLASTIC QUAD FLAT PACK (PQFP) .547 BSC SQ. (13.9) See Detail A .097 max (2.45) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8599 PACKAGE DIMENSIONS .394 BSC SQ. (10.0) .079 +.004 / -.002 (2.00 +.10 / -.05) .008 (.13) HOLT INTEGRATED CIRCUITS 14 inches (millimeters) Package Type: 44PQS ...