hi-8599 Holt Integrated Circuits, Inc., hi-8599 Datasheet - Page 2

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hi-8599

Manufacturer Part Number
hi-8599
Description
Transmitter With Line Driver And Dual Receivers
Manufacturer
Holt Integrated Circuits, Inc.
Datasheet
PIN DESCRIPTION
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
TXA(OUT)
TXB(OUT)
SIGNAL
CWSTR
TX CLK
ENTX
BD15
BD14
BD13
BD12
BD10
BD09
BD08
BD07
BD06
BD05
BD04
BD03
BD02
BD01
BD00
TEST
BD11
D/R1
D/R2
GND
TX/R
EN1
EN2
CLK
V
SEL
PL1
PL2
MR
V+
V-
CC
FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
+5V ±5%
+9.5V to +10.5V
-9.5V to -10.5V
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0 V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow
Line driver output - A side
Line driver output - B side
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
Disable Transmitter output if high (pull-down)
HOLT INTEGRATED CIRCUITS
HI-8599
DESCRIPTION
2
EN1
is high
PL1
.

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