hip0060 Intersil Corporation, hip0060 Datasheet
hip0060
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hip0060 Summary of contents
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... Quad Low Side Power Driver with Serial Bus Control and Fault Protection Description The HIP0060 logic controlled Quad Low Side Power Driver. The outputs are individually protected for over-current (OC), over-temperature (OT) and over-voltage (OV short circuit in the output load is sensed (I power driver, that output current will be independently limited while the other outputs remain in operation ...
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... Low Output Voltage Input Pull-Down Current, INx I INPD Reset Input Pull-Up Current, RST I RPU HIP0060 Thermal Information Thermal Resistance (Typical, Notes SOIC - PC Board Mount, Min. Copper . . . . . . . . . . CL SOIC - PC Board Mount, 2 sq. in. Copper . . . . . . . . Maximum Storage Temperature Range -55 Maximum Lead Temperature (Soldering 10s 300 ...
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... Also, as shown in the Block Diagram, the OT fault status bit information is ORed into a one-shot that drives an open drain to provide an INT interrupt signal out- put. The INT output has a specified timing from the one-shot multi and is defined in the Electrical Specifications as t HIP0060 0V - 125 C ...
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... RST INA INB INC IND FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR MOTORS OR STEPPER MOTORS HIP0060 HIP0060 devices may be linked in cascade for the purposes of SPI control. Serial data is clocked in and out of each HIP0060 and then back to the host microcontroller. All linked devices have a common control sequence ...
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... REFER TO THE TIMING TEST CIRCUIT 10000 1000 100 10 0.1 FIGURE 3. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, T HIP0060 V +5V DD 4.7k OUTA RST INA OUTB INB HIP0060 OUTC (TIMING TEST INC CIRCUIT) IND OUTD GND INT 90% 10% SAFE OPERATING AREA ...
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... SI xxxxxxxx SO (THREE-STATE) FIGURE 5. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET. REFER TO THE ELECTRICAL SPECIFICATION FOR THE HIGH AND LOW INPUT AND OUTPUT THRESHOLD LEVELS SHOWN FOR TIMING REFERENCE HIP0060 MSB INTERNAL STROBE FOR DATA CAPTURE FIGURE 4. DATA AND CLOCK TIMING DIAGRAM ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HIP0060 M24.3 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...