hip0060 Intersil Corporation, hip0060 Datasheet - Page 4

• Manufacturer Part Number: hip0060
• Description: 1.5a, 50v Quad Low Side Power Driver With Serial Bus Control And Fault Protection
• Manufacturer: Intersil Corporation

Serial Diagnostic Link
A serial diagnostic link via the SPI bus provides the means
to clock fault data in and out of the fault register to the micro-
controller. When the microcontroller receives an INT inter-
rupt signal, data is clocked from the Serial Diagnostic
Register to determine what fault bit has been set. Appropri-
ate action for the fault may then be taken, as defined by the
programming of the microcontroller.
Serial Diagnostic Register
Fault bits consist of one OT bit and one OL bit for each
switching channel (A, B, C and D). Data is transferred out
of SO MSB first on the rising edge of SCK after CS goes
low. Data is shifted into the input shift register on the falling
edge of SCK. The defined order of the DO0 to DO7 fault
bits is as follows:
FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
BIT
MOTORS OR STEPPER MOTORS
NAME
OTA
OTB
OTC
OTD
OLC
OLD
OLA
OLB
OT in Output Driver A, T
OT in Output Driver B, T
OT in Output Driver C, T
OT in Output Driver D, T
OL in Output Driver A, OFF Load > R
OL in Output Driver B, OFF Load > R
OL in Output Driver C, OFF Load > R
OL in Output Driver D, OFF Load > R
CONDITION REQUIRED TO SET BIT
4.7k
RST
INA
INB
INC
IND
INT
J
J
J
J
HIP0060
T
T
T
T
LIM
LIM
LIM
LIM
V
DD
+5V
OLD
OLD
OLD
OLD
HIP0060
OUTB
OUTD
OUTA
OUTC
4
HIP0060 devices may be linked in cascade for the purposes
of SPI control. Serial data is clocked in and out of each
HIP0060 and then back to the host microcontroller. All linked
devices have a common control sequence. When CS goes
low, fault data is shifted to the Serial Diagnostic Register.
SCK must be low when CS goes low. Also, when CS goes
low, SO changes from a three-state to a low state and
remains low until SCK goes high. Serial data is transferred
by SCK. After the serial data is transferred, SCK must
remain low as CS goes high. The serial data transfer must
be a continuous sequence while CS is low.
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) bus is system con-
trolled by a host micro. The SPI bus controls the Serial Diag-
nostic Link with the CS (Chip Select), SCK, SI, SO and RST
(Reset) lines. Figures 4 and 5 define the timing and protocol
for the bus.
Reset Operation
The RST input is an active low reset input. When RST is low,
the internal diagnostic flags are cleared but not the shift reg-
ister. When RST is low, all outputs and output switches are
disabled. To clear the shift register, CS is switched from high
to low during or after a reset while there are no active faults,
jamming data from the cleared fault flags into the shift regis-
tor. The RST input has an internal pull-up to sustain a logic
high when floating.
The V
POR function. When the V
threshold, the output drivers are shutoff. To insure that the
diagnostic link shift register is correct after V
V
DD(POR)
DD
input is the power supply to the 5V logic and the
, a manual reset must be executed.
SOLENOID
RELAY
MOTOR
LAMP
M
DD
V
V
is less than the V
BATT
BATT
DD
is less than
DD(POR)