hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet - Page 4

• Manufacturer Part Number: hi-3588pqt
• Description: Receiver With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3588 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction
0B hex. Each bit of the Control Register has the following function:
(MSB)
(LSB)
CR10
CR11 ARINC Label
CR12
CR13
CR14
CR15
CR0
CR1 ARINC Clock
CR2 Enable Label
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR
Bit FUNCTION STATE
Source Select
Parity Check
Recognition
Data Rate
Definition
Bit Order
Receiver
Receiver
Receiver
Receiver
Decoder
RFLAG
Enable
Enable
Select
-
-
-
-
-
-
-
-
0
1
0
1
0
1
X
0
1
0
1
0
1
X
X
0
1
X
X
X
0
1
-
-
ARINC bits 10 and 9 must match CR7 and CR8
Data rate = CLK/10
Data rate = CLK/80
FLAG goes high when receive FIFO is empty
RFLAG goes high when receive FIFO is full
ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
Disable receiver. The HI-3588 ignores
Label bit order reversed (SeeTable 2)
ARINC CLK = ACLK input frequency
the ARINC bit 10 must match this bit
the ARINC bit 9 must match this bit
Receiver odd parity check enabled
Label bit order same as received
Receiver parity check disabled
If receiver decoder is enabled,
If receiver decoder is enabled,
all ARINC 429 data bus traffic
Receiver decoder disabled
Label recognition disabled
Label recognition enabled
DESCRIPTION
Normal operation
(See Table 2)
Not used
Not used
Not used
Not used
Not used
Not used
(ARINC 429 High-Speed)
(ARINC 429 Low-Speed)
HOLT INTEGRATED CIRCUITS
HI-3588
4
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
received ARINC word are mapped to the HI-3588 SPI data word
bits during data read or write operations. The following table
describes this mapping:
STATUS REGISTER
The HI-3588 contains an 8-bit Status Register which can be
interrogated to determine status of the ARINC Receive FIFO. The
Status Register is read using SPI instruction 0A hex. Unused bits
are undefined and may be read as either “1” or “0”. The following
table defines the Status Register bits.
ARINC bit 8
ARINC bit 1
CR11=0
(MSB)
Cr11=1
(LSB)
SR0
SR1
SR2
SR3
SR4
SR5
SR6
SR7
SR
Bit
SPI
bit
FUNCTION
Receive FIFO
Receive FIFO
Receive FIFO
1
Not used
Not used
Not used
Not used
Not used
Half Full
Empty
Full
2
7
2
3
6
3
Table 2. SPI / ARINC bit-mapping
4
5
4
STATE
5
4
5
X
X
X
0
1
0
1
0
1
0
0
6
3
6
7
2
7
Receiver FIFO contains valid data
Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=”0”
Receiver FIFO is empty
Receiver FIFO holds less than 16
words
Receiver FIFO holds at least 16
words
Receiver FIFO not full. RFLAG pin
reflects the state of this bit when
CR15=”1”
Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
Undefined
Undefined
Undefined
Always “0”
Always “0”
8
1
8
9
9
9
DESCRIPTION
10
10
10
11 - 31
11 - 31
11 - 31
Data
Data
32
32
32