hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet - Page 3

• Manufacturer Part Number: hi-3588pqt
• Description: Receiver With Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3588A. When
an instruction op code into the decoder, starting with the first
positive edge. The op code is fed into the SI pin, most significant bit
first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
data field bit-length varies with read instruction type.
OP CODE
Hex
0A
0B
0C
0D
0E
00
01
02
03
04
05
06
07
08
09
0F
10
CS
DATA FIELD
goes low, the next 8 clocks at the SCK pin shift
256 bits
variable
256 bits
32 bits
16 bits
16 bits
None
None
None
None
8 bits
8 bits
8 bits
8 bits
8 bits
None
None
No instruction implemented
After the 8th op-code bit is received, perform Master Reset (MR)
After the 8th op-code bit is received
After the 8th op-code bit is received
Reset label at address specified in data field
Set label at address specified in data field
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and
FC hex and reset label FE hex.
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable
values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in
no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock.
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
Dump the Receive FIFO. No framing. If
be zeros.
Read the Status Register
Read the Control Register
Read the ACLK divide value programmed previously using op code 07 hex
Read the Label look-up memory table consecutively starting with address FF hex
No instruction implemented
No instruction implemented
Write the Control Register
TABLE 1. DEFINED INSTRUCTION OP CODES
HOLT INTEGRATED CIRCUITS
HI-3588
3
, reset all label selections
, set all the label selections
Table 1 lists all instructions. Instructions that perform a reset or set
are executed after the last SI bit is received while
Example:
CS
SCK
SI
CS
DESCRIPTION
held low after last word, the data will
MSB
op code 07hex
one SPI Instruction
LSB MSB
data field 02hex
CS
LSB
is still low.