hi-3588pqt Holt Integrated Circuits, Inc., hi-3588pqt Datasheet - Page 2

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hi-3588pqt

Manufacturer Part Number
hi-3588pqt
Description
Receiver With Spi Interface
Manufacturer
Holt Integrated Circuits, Inc.
Datasheet
BLOCK DIAGRAM
PIN DESCRIPTIONS
SIGNAL FUNCTION
RINB-40
RINA-40
RFLAG
ACLK
RINB
RINA
GND
VDD
SCK
MR
CS
SO
SI
RINA-40
RINB-40
ACLK
RINA
RINB
SCK
CS
SO
OUTPUT
OUTPUT
SI
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
40 Kohm
40 Kohm
ARINC receiver negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears the Receiver data FIFO and flags
SPI interface serial data input
Chip select. Data is shifted into SI and out of SO when
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip 0V supply. Note BOTH GND pins MUST be connected
Master timing source for the ARINC 429 receiver
SPI interface serial data output
Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1)
3.3V or 5.0V logic power
Alternate ARINC receiver positive input. Requires external 40K ohm resistor
ARINC receiver positive input. Direct connection to ARINC 429 bus
Interface
SPI
Control Register
Line Receiver
ARINC 429
Divider
ARINC
Clock
HOLT INTEGRATED CIRCUITS
ARINC 429
Valid word
Checker
DESCRIPTION
Status Register
HI-3588
2
VDD
GND
Memory
Bit Map
Label
Label
Filter
Filter
CS
is low.
ARINC 429
Data FIFO
Received
PULL UP / DOWN
10K ohm pull-down
10K ohm pull-down
10K ohm pull-up
10K ohm pull-down
10K ohm pull-down
RFLAG

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