at52br3244 ATMEL Corporation, at52br3244 Datasheet
at52br3244
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at52br3244 Summary of contents
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... Flash + 4-megabit (256K x 16)/ 8-megabit (512K x 16) SRAM Stack Memory AT52BR3244 AT52BR3244T AT52BR3248 AT52BR3248T Not Recommended for New Designs. New Designs Should Use AT52BR3224(T)/3228(T) Rev. 2471E–STKD–10/02 1 ...
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... AT52BR3244(T)/ AT52BR3248(T) (Top View) Pin Configurations l AT52BR3244(T)/3248( A20 A11 A15 B A16 A8 A10 C WE RDY/BSY D SGND RESET E NC VPP A19 F SLB SUB SOE G A18 A17 Pin Name Function A0 - A20 Addresses CE Flash Chip Enable OE Flash Output Enable ...
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... Description The AT52BR3244(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM in a stacked 66-ball CBGA package. The AT52BR3248(T) combines a 32-megabit Flash (2M x 16) and a 8-megabit SRAM in a stacked 66-ball CBGA package. The devices operate at 2.7V to 3.3V in the industrial temperature range. They use a 32-megabit Flash with dual plane architecture for concurrent read/write operations ...
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... It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. AT52BR3244(T)/3248( 5.0V or 12.0V, the pro- PP ...
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... Flash Memory Block Diagram OUTPUT BUFFER INPUT A0 - A20 BUFFER ADDRESS LATCH Y-DECODER X-DECODER 2471E–STKD–10/02 AT52BR3244(T)/3248(T) I/O0 - I/O15/A-1 INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER COMMAND REGISTER DATA COMPARATOR WRITE STATE MACHINE Y-GATING PLANE B SECTORS PLANE A SECTORS RESET RDY/BUSY ...
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... If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after AT52BR3244(T)/3248( ...
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... input signal. When the V PP must be in the 5V ± 0.5V or 12V ± 0.5V range to ensure PP pin can be left unconnected. pp AT52BR3244(T)/3248(T) supply for programming CC supply, the device will CC input and the V power supply ...
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... Flash in the following ways: (a) V below 1.8V (typical), the program function is inhibited. (b) V has reached the V before programming. (c) Program inhibit: holding any one of OE low, CE high or WE AT52BR3244(T)/3248(T) 8 sense level, the device will automatically time out 10 ms (typical) CC ...
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... inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0.6V. 2471E–STKD–10/02 AT52BR3244(T)/3248( ...
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... Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0. Voltage on OE and V PP with Respect to Ground ...................................-0.6V to +13.0V AT52BR3244(T)/3248(T) 10 (1) 2nd Bus 3rd Bus Cycle Cycle Data Addr Data ...
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... All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A20 - 2471E–STKD–10/ AT52BR3244(T)/3248( ...
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... AT52BR3244(T)/3248(T) 12 Sector Size (Words) SA0 4K SA1 4K SA2 4K SA3 4K SA4 4K SA5 4K SA6 4K SA7 4K SA8 32K SA9 32K SA10 32K SA11 32K SA12 32K SA13 32K ...
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... SA65 32K SA66 32K SA67 32K SA68 32K SA69 32K SA70 32K AT52BR3244(T)/3248(T) x16 Address Range (A20 - A0) F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF ...
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... SA24 B SA25 B SA26 B SA27 B SA28 B SA29 B SA30 B SA31 B SA32 B SA33 B SA34 B SA35 B SA36 AT52BR3244(T)/3248(T) 14 Size (Words) Address Range (A20 - A0) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K ...
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... SA60 A SA61 A SA62 A SA63 A SA64 A SA65 A SA66 A SA67 A SA68 A SA69 A SA70 2471E–STKD–10/02 AT52BR3244(T)/3248(T) Size (Words) Address Range (A20 - A0) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K ...
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... Refer to AC programming waveforms on page 23 12.0V ± 0.5V Manufacturer Code: 001FH, Device Code: 00D8H - AT4952BR3244/3248; 00D9H - AT52BR3244T/3248T. 5. See details under “Software Product Identification Entry/Exit” on page 24. can be left unconnected or 0V ≤ 12V ± 0.5V. AT52BR3244(T)/3248(T) 16 AT52BR3244(T)-85, 90 Ind. ...
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... MHz OUT = 5.0V ± 0.5V) = 5.0V ± 0.5V) = 12.0V ± 0.5V) = 12.0V ± 0. -400 µ -100 µA OH AT52BR3244(T)/3248(T) Min Max -10 2.0 0.45 0.20 2.4 2.5 Units 10 µA 10 µA 10 µ µ µA 50 µ ...
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... ADDRESS VALID tCE tOE tACC tRO HIGH Z OUTPUT VALID - t after the address transition without impact on t ACC after the falling edge of CE without impact ACC AT52BR3244(T)/3248(T)-110 Max Min 600 tDF tOH . ACC . Max Units ...
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... Input Test Waveforms and Measurement Level t Output Test Load Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% tested. 2471E–STKD–10/ < Max 6 12 AT52BR3244(T)/3248(T) Units Conditions OUT 19 ...
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... Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH AC Word Load Waveforms WE Controlled CE Controlled AT52BR3244(T)/3248(T) 20 Min Max Units ...
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... 2471E–STKD–10/02 < 4.5V) PP > 4.5V) PP < 4.5V) PP > 4.5V) PP < 4.5V) PP > 4.5V) PP PROGRAM CYCLE WPH t DH 555 AAA ADDRESS AT52BR3244(T)/3248(T) Min Typ Max 500 200 10 5 200 400 100 150 SR/W VALID ...
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... For chip erase, the address should be 555. For sector erase, the address depends on what sector erased. (See note 3 under Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. AT52BR3244(T)/3248( WPH ...
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... Any address location may be used but the address should not vary. 2471E–STKD–10/02 (1) t OEH tDH t HIGH ( OEH OEHP HIGH Z AT52BR3244(T)/3248(T) Min Typ Max Min Typ Max 10 10 150 Units ns ...
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... The device does not remain in identification mode if pow- ered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH(x16) Device Code: 00D8H- AT52BR3244/3248; 00D9H-AT52BR3244T/3248T. 6. Either one of the Product ID Exit commands can be used. AT52BR3244(T)/3248(T) 24 Sector Lockdown Enable Algorithm LOAD DATA F0 TO ...
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... Plane B 2471E–STKD–10/02 Status Bit I/O7 Plane B Plane A DATA TOGGLE I/O7 DATA 0 DATA TOGGLE 0 DATA DATA DATA DATA TOGGLE I/O7 DATA AT52BR3244(T)/3248(T) I/O6 I/O2 Plane B Plane A DATA 1 TOGGLE DATA DATA TOGGLE TOGGLE DATA 1 TOGGLE DATA DATA DATA TOGGLE TOGGLE DATA Plane B DATA 1 DATA ...
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... This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. Features • • • Block Diagram AT52BR3244(T)/3248(T) 26 Fully Static Operation and Tri-state Output TTL Compatible Inputs and Outputs Battery Backup – 1.2V (Min) Data Retention Current/I Voltage (V) Speed (ns) 2 ...
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... Output Disabled Write Read Min 2.7 0 2.2 (1) -0.31 AT52BR3244(T)/3248(T) Unit V V °C °C 1.0 W I/O Pin I/O0 - I/O7 I/O8 - I/O15 High-Z High-Z High-Z High-Z D High-Z IN High High High-Z OUT High-Z D OUT ...
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... T CC (1) Capacitance (Temp = 25° 1.0 MHz) Symbol Parameter C Input Capacitance (Add, SCS1, IN SCS2, SLB, SUB, SWE, SOE) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. AT52BR3244(T)/3248(T) 28 Test Condition V < V < < V < OUT CC SCS1 = V ...
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... TA = -40°C to 85°C, Unless Otherwise Specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load TTL Load TTL Load 2471E–STKD–10/02 AT52BR3244(T)/3248( Min Max ...
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... AC Test Loads Note: AT52BR3244(T)/3248( OUT (1) CL Including jig and scope capacitance 1.8V TM 4091 Ohm 3273 Ohm 2471E–STKD–10/02 ...
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... Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. 2471E–STKD–10/02 AT52BR3244(T)/3248( ...
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... Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. AT52BR3244(T)/3248(T) 32 (1),(4),(8) ...
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... IN SS Chip Deselect to Data Retention Time = 25°C. Typical values are sampled and not 100% tested. A DATA RETENTION MODE VCC 2.7V t CDR IH VDR SCS1 > VCC - 0.2V SCS1 VSS DATA RETENTION MODE t CDR SCS2 < 0.2V AT52BR3244(T)/3248(T) Min Typ Max 1.2 3 Unit V µ ...
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... This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. Features • • • Block Diagram AT52BR3244(T)/3248(T) 34 Fully Static Operation and Tri-state Output TTL Compatible Inputs and Outputs Battery Backup – 1.2V (Min) Data Retention Current/I Voltage (V) Speed (ns) 2 ...
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... Output Disabled Write Read Min 2.7 0 2.2 (1) -0.31 AT52BR3244(T)/3248(T) Unit V V °C °C 1.0 W I/O Pin I/O0 - I/O7 I/O8 - I/O15 High-Z High-Z High-Z High-Z D High-Z IN High High High-Z OUT High-Z D OUT ...
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... These parameters are sampled and not 100% tested. AC Characteristics T = -40°C to 85°C, Unless Otherwise Specified A # Symbol Parameter 1 t Read Cycle Time Address Access Time Chip Select Access Time ACS AT52BR3244(T)/3248(T) 36 Test Condition V < V < < V < OUT CC SCS1 = V or SCS2 ...
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... TA = -40°C to 85°C, Unless Otherwise Specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load TTL Load TTL Load 2471E–STKD–10/02 AT52BR3244(T)/3248( Min Max ...
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... AC Test Loads Note: AT52BR3244(T)/3248( OUT (1) CL Including jig and scope capacitance 2.8V TM 1045 Ohm 2048 Ohm 2471E–STKD–10/02 ...
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... Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. 2471E–STKD–10/02 AT52BR3244(T)/3248( ...
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... Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. AT52BR3244(T)/3248(T) 40 (1),(4),(8) ...
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... IN SS Chip Deselect to Data Retention Time = 25°C. Typical values are sampled and not 100% tested. A DATA RETENTION MODE VCC 2.7V t CDR IH VDR SCS1 > VCC - 0.2V SCS1 VSS DATA RETENTION MODE t CDR SCS2 < 0.2V AT52BR3244(T)/3248(T) Min Typ Max 1.2 3 Unit V µ ...
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... Ordering Information t ACC (ns) Ordering Code 85 AT52BR3244-85CI 90 AT52BR3244-90CI 110 AT52BR3244-11CI 85 AT52BR3244T-85CI 90 AT52BR3244T-90CI 110 AT52BR3244T-11CI 85 AT52BR3248-85CI 90 AT52BR3248-90CI 85 AT52BR3248T-85CI 90 AT52BR3248T-90CI 66C4 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BR3244(T)/3248(T) 42 Flash Boot Flash Plane Block Architecture SRAM Bottom 24M + 8M 256K x 16 Bottom 24M + 8M ...
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... Ball Corner 1.20 REF Øb 66C4, 66-ball ( Array 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT52BR3244(T)/3248(T) 0.12 C Seating Plane Side View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – – 1.20 A1 0.25 – ...
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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...