at52br3244 ATMEL Corporation, at52br3244 Datasheet - Page 8

• Manufacturer Part Number: at52br3244
• Description: 32-megabit 2m X 16 Flash +4-megabit 256k X 16 / 8-megabit 512k X 16 Sram Stack Memory
• Manufacturer: ATMEL Corporation

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see “Operating Modes” on page 16 (for hardware operation) or “Software
Product Identification Entry/Exit” on page 24. The manufacturer and device codes are
the same for both modes.
128-BIT PROTECTION REGISTER: The 32-megabit Flash contains a 128-bit register
that can be used for security purposes in system design. The protection register is
divided into two 64-bit blocks. The two blocks are designated as block A and block B.
The data in block A is non-changeable and is programmed at the factory with a unique
number. The data in block B is programmed by the user and can be locked out such that
data in the block cannot be reprogrammed. To program block B in the protection regis-
ter, the four-bus cycle Program Protection Register command must be used as shown in
the Command Definition table on page 10. To lock out block B, the four-bus cycle Lock
Protection Register command must be used as shown in the Command Definition table.
Data bit D0 must be one during the fourth bus cycle. All other data bits during the fourth
bus cycle are don’t cares. Please see the “Protection Register Addressing Table” on
page 11 for the address locations in the protection register. To read the protection regis-
ter, the Product ID Entry command is given followed by a normal read operation from an
address within the protection register. After reading the protection register, the Product
ID Exit command must be given prior to performing any other operation.
DATA POLLING: The Flash features Data Polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last word loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may begin. During a chip or sector
erase operation, an attempt to read the device will give a “0” on I/O7. Once the program
or erase cycle has completed, true data will be read from the device. Data Polling may
begin at any time during the program cycle. Please see “Status Bit Table” on page 25 for
more details.
TOGGLE BIT: In addition to Data Polling, the 32-megabit Flash provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the same memory plane will result in
I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the toggle bit may begin at any time
during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the
toggle bit that is available on I/O6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the I/O2 bit toggling. Please see
“Status Bit Table” on page 25 for more details.
RDY/BUSY: An open-drain Ready/Busy output pin provides another method of detect-
ing the end of a program or erase operation. RDY/BUSY is actively pulled low during the
internal program and erase cycles and is released at the completion of the cycle. The
open-drain connection allows for OR-tying of several devices to the same RDY/BUSY
line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects
against inadvertent programs to the Flash in the following ways: (a) V
sense: if V
is
CC
CC
below 1.8V (typical), the program function is inhibited. (b) V
power-on delay: once V
CC
CC
has reached the V
sense level, the device will automatically time out 10 ms (typical)
CC
before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
AT52BR3244(T)/3248(T)
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