m36l0t8060b1 STMicroelectronics, m36l0t8060b1 Datasheet - Page 10

• Manufacturer Part Number: m36l0t8060b1
• Description: 256 Mbit 16 Mb , Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Psram, 1.8 V Core, 3 V I/o Supply, Multichip Package
• Manufacturer: STMicroelectronics

Signal descriptions
2.6
2.7
2.8
2.9
2.10
2.11
10/22
Flash Write Protect (WP
Write Protect is an input that provides additional hardware protection for each block. When
Write Protect is Low, V
blocks cannot be changed. When Write Protect is at High, V
the locked-down blocks can be locked or unlocked. (See the lock status table in the
M30L0T8000x2 datasheet).
Flash Reset (RP
The Reset input provides a hardware reset of the Flash memory. When Reset is at V
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the reset supply current I
value of I
reset. When Reset is at V
device enters asynchronous read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
Flash Latch Enable (L
Latch Enable latches the A0-A23 address bits on its rising edge. The address latch is
transparent when Latch Enable is at V
Flash Clock (K
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V
read and in write operations.
Flash Wait (WAIT
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at V
Enable is at V
one data cycle in advance.
PSRAM Chip Enable (E1
When asserted (Low), the Chip Enable, E1
buffers and decoders, allowing Read and Write operations to be performed. When de-
asserted (High), all other pins are ignored and the device is automatically put in low-power
standby mode.
It is not allowed to set E
DD2
. After reset all blocks are in the locked state and the configuration register is
IH
, or Reset is at V
F
IL
)
F
, lock-down is enabled and the protection status of the locked-down
F
F
to V
)
IH
)
, the device is in normal operation. Upon exiting reset mode the
IL
, E1
IL
F
. It can be configured to be active during the wait cycle or
)
P
F
DD2
P
to V
)
)
IL
. Refer to the M30L0T8000x2 datasheet for the
and it is inhibited when Latch Enable is at V
IL
P
and E2
, activates the memory state machine, address
IL
. Clock is ignored during asynchronous
P
to V
IH
M36L0T8060T1, M36L0T8060B1
at the same time.
IH
, lock-down is disabled and
IH
, Output
IH
IL
.
, the