m36l0t8060b1 STMicroelectronics, m36l0t8060b1 Datasheet - Page 9

• Manufacturer Part Number: m36l0t8060b1
• Description: 256 Mbit 16 Mb , Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Psram, 1.8 V Core, 3 V I/o Supply, Multichip Package
• Manufacturer: STMicroelectronics

M36L0T8060T1, M36L0T8060B1
2
2.1
2.2
2.3
2.4
2.5
Signal descriptions
See
connected to this device.
Address inputs (A0-A23)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The
other lines (A23-A22) are only inputs for the Flash memory component.
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the Flash memory Program/Erase Controller or they select the cells to be
accessed in the PSRAM.
In the PSRAM these signals are also used during the set configuration register sequence
Data inputs/outputs (DQ0-DQ15)
In the Flash memory the data I/O output the data stored at the selected address during a
bus read operation or input a command or the data to be programmed during a bus write
operation.
For the PSRAM component, the upper byte data inputs/outputs (DQ8-DQ15) carry the data
to or from the upper part of the selected address when Upper Byte Enable (UB
Low. The lower byte data inputs/outputs (DQ0-DQ7) carry the data to or from the lower part
of the selected address when Lower Byte Enable (LB
LB
Flash Chip Enable (E
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component. When Chip Enable is Low, V
High, V
deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
It is not allowed to set E
Flash Output Enable (G
The Output Enable pin controls the data outputs during Flash memory bus read operations.
Flash Write Enable (W
The Write Enable input controls the bus write operation of the Flash memory’s command
interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
P
Figure 1: Logic diagram
are disabled, the data inputs/ outputs are high impedance.
IH
, the device is in active mode. When Chip Enable is at V
F
to V
and
IL
, E1
F
)
F
Table 1: Signal names
)
P
F
)
to V
IL
and E2
P
to V
P
) is driven Low. When both UB
for a brief overview of the signals
IH
at the same time.
IH
the Flash memory is
Signal descriptions
IL
, and Reset is
P
) is driven
P
and
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