m36llr8760d1 STMicroelectronics, m36llr8760d1 Datasheet - Page 7

• Manufacturer Part Number: m36llr8760d1
• Description: 256 + 128 Mbit Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: STMicroelectronics

SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A23). Addresses
are common inputs for the Flash memory and
PSRAM components. A22 is common to the two
Flash memory components whereas A23 is an ad-
dress input for the 256 Mbit Flash memory compo-
nent only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the
internal state machine. The Flash memories are
accessed through the Chip Enable signal (E
through the Write Enable signal (W
PSRAM is accessed through the Chip Enable sig-
nal (E
It is not allowed to have E
same time.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Bus Write op-
eration.
For the PSRAM component, the upper Byte Data
Inputs/Outputs (DQ8-DQ15) carry the data to or
from the upper part of the selected address when
Upper Byte Enable (UB
Byte Data Inputs/Outputs (DQ0-DQ7) carry the
data to or from the lower part of the selected ad-
dress when Lower Byte Enable (LB
Low. When both UB
Data Inputs/ Outputs are high impedance.
Latch Enable (L). The Latch Enable pin is com-
mon to the Flash memory and PSRAM compo-
nents.
For details of how the Latch Enable signal be-
haves, please refer to the datasheets of the re-
spective memory components: M69KB096AA for
the
M58LR128GT/B for Flash 1 and Flash 2, respec-
tively.
Clock (K). The Clock input pin is common to the
Flash memory and PSRAM components.
For details of how the Clock signal behaves,
please refer to the datasheets of the respective
memory components: M69KB096AA for the
PSRAM
M58LR128GT/B for Flash 1 and Flash 2, respec-
tively.
Figure 2., Logic Diagram
P
PSRAM
) and the Write Enable signal (W
and
and
P
M30L0R8000(T/B)0
and LB
P
M30L0R8000(T/B)0
) is driven Low. The lower
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
F
Low, and E
and
P
are disabled, the
Table 1., Signal
F
P
P
), while the
) is driven
Low at the
P
).
A0-A21
F
) and
and
and
Wait (WAIT). WAIT is an output pin common to
the Flash memory and PSRAM components. How-
ever the WAIT signal does not behave in the same
way for the PSRAM and the Flash memories.
For details of how it behaves, please refer to the
M69KB096AA datasheet for the PSRAM and to
the
datasheets for Flash 1 and Flash 2, respectively.
Flash Chip Enable Inputs (E
Flash Chip Enable inputs activate the control logic,
input buffers, decoders and sense amplifiers of the
Flash memory component selected (E
select Flash 1, E
When Chip Enable is Low, V
V
able is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the standby
level.
It is not allowed to have E
E
ponent can be enabled at a time.
Flash Output Enable Inputs (G
Output Enable pins control the data outputs during
Flash memory Bus Read operations.
Flash Write Enable (
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
disabled and the Locked-Down blocks can be
locked or unlocked. (See the Lock Status Table in
the M30L0R8000(T/B)0 and M58LR128GT/B
datasheets).
Flash Reset (RP
hardware reset of the Flash memories. When Re-
set is at V
puts are high impedance and the current
consumption is reduced to the Reset Supply Cur-
rent I
istics -
all blocks are in the Locked state and the Configu-
ration Register is reset. When Reset is at V
device is in normal operation. Exiting Reset mode
the device enters Asynchronous Read mode, but
IH
P
at V
, the device is in active mode. When Chip En-
DD2
M30L0R8000T/B0
IL
Currents, for the value of I
. Refer to
at the same time. Only one memory com-
IL
IH
, the memory is in Reset mode: the out-
the corresponding Flash memory are
F
F2
Table 6., Flash 1 DC Character-
). The Reset input provides a
is used to select Flash 2).
W
F
). The
F
F1
). Write Protect is an
and
IL
at V
F1
, and Reset is High,
, E
F1
IL
IH
DD2
M58LR128GT/B
, E
Write
, G
F2
, Lock-Down is
). The
. After Reset
F2
F1
F2
at V
). The
is used to
Enable
IH
IL
, the
7/19
and
IL
,