m36llr8760d1 STMicroelectronics, m36llr8760d1 Datasheet - Page 8

• Manufacturer Part Number: m36llr8760d1
• Description: 256 + 128 Mbit Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: STMicroelectronics

M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
a negative transition of Chip Enable or Latch En-
able is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
(refer to
teristics -
PSRAM Chip Enable input (E
able input activates the PSRAM when driven Low
(asserted). When deasserted (V
disabled, and goes automatically in low-power
Standby mode or Deep Power-down mode.
PSRAM Write Enable (W
controls the Bus Write operation of the PSRAM.
When asserted (V
and Write operations can be performed either to
the configuration registers or to the memory array.
PSRAM Output Enable (G
G
ing fast read/write cycles to be achieved with the
common I/O data bus.
PSRAM Upper Byte Enable (UB
Byte En-able, UB
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LB
Byte Enable, LB
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
If both LB
operation, the device will disable the data bus from
receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active
mode as long as E
PSRAM Configuration Register Enable (CR
When this signal is driven High, V
tions load either the value of the Refresh Configu-
ration Register (RCR) or the Bus configuration
register (BCR).
V
V
8/19
DDF1
DDF2
P
, provides a high speed tri-state control, allow-
/V
provide the power supply to the internal
Table 8., Flash 1 and Flash 2 DC Charac-
DDF2
Voltages).
P
and UB
Supply Voltages. V
P
P
, gates the data on the Lower
IL
P
P
, gates the data on the Upper
), the device is in Write mode
remains Low.
are disabled (High) during an
P
). Write Enable, W
P
). Output
P
). The Chip En-
IH
P
P
IH
), the device is
). The
DDF1
). The
, Write opera-
Enable,
Upper
Lower
RPH
and
P
P
).
,
cores of Flash 1 and Flash 2, respectively. It is the
main power supply for all Flash memory opera-
tions (Read, Program and Erase).
V
supply to the internal core of the PSRAM device. It
is the main power supply for all PSRAM opera-
tions.
V
power supply for the Flash memory. This allows all
Outputs to be powered independently of the Flash
memory and SRAM core power supplies, V
and V
V
control input and a power supply pin for the Flash
memories. The two functions are selected by the
voltage range applied to the pin.
If V
V
age lower than V
against Program or Erase, while V
ables these functions (see Tables
Characteristics for the relevant values). V
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If V
supply pin. In this condition V
until the Program/Erase algorithm is completed.
V
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips. It must
be connected to the system ground.
Note: Each Flash memory device in a system
should have their supply voltage (V
the program supply voltage V
with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca-
pacitors should be as close as possible to the
package). See
Load
sufficient to carry the required V
and erase currents.
CCP
DDQF
PPF
PPF
SS
PPF
PPF
Ground. V
is seen as a control input. In this case a volt-
Program Supply Voltage. V
Supply Voltage. V
CCP
Circuit. The PCB track widths should be
Supply Voltage. V
is kept in a low voltage range (0V to V
is in the range of V
.
SS
PPLK
Figure 6., AC Measurement
is the common ground refer-
gives an absolute protection
CCP
PPH
DDQF
PPF
provides the power
it acts as a power
PPF
PPF
must be stable
provides
PPF
PPF
6
decoupled
and 8, DC
> V
DDF
is both a
program
PP1
PPF
DDQF
) and
DDF
en-
the
is
)