k4t51043qe-zlcc Samsung Semiconductor, Inc., k4t51043qe-zlcc Datasheet - Page 24

• Manufacturer Part Number: k4t51043qe-zlcc
• Description: 512mb E-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

15.0 Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing.
2. AL = Additive Latency.
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied.
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.
5. Timings are specified with command/address input slew rate of 1.0 V/ns.
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in
8. Data setup and hold time derating.
Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe
Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe
K4T51043QE
K4T51083QE
K4T51163QE
Siew
Slew
V/ns
V/ns
rate
rate
DQ
DQ
tXARDS is expected to be used for slow active power down exit timing.
differential strobe mode and a slew rate of 1.0 V/ns in single ended mode.
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
125
100
83
67
0
4.0 V/ns
0
4.0 V/ns
-
-
-
-
-
-
-
-
-
-
-
-
∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, the note applies to entire Table)
∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, the note applies to entire Table)
45
21
45
21
0
0
-
-
-
-
-
-
-
-
-
-
-
-
125
100
-11
67
83
-5
0
0
3.0 V/ns
3.0 V/ns
-
-
-
-
-
-
-
-
-
-
-14
-14
45
21
45
21
0
0
-
-
-
-
-
-
-
-
-
-
100
125
-25
-13
-11
83
67
-5
0
0
2.0 V/ns
2.0 V/ns
-
-
-
-
-
-
-
-
-14
-31
-14
-31
45
21
45
21
0
0
-
-
-
-
-
-
-
-
-10
-13
-31
79
12
95
12
-1
7
1
1.8 V/ns
-
-
-
-
1.8 V/ns
-
-
-
-
DQS,DQS Differential Slew Rate
DQS,DQS Differential Slew Rate
24 of 45
-19
-42
-19
-42
33
12
33
12
-2
-2
-
-
-
-
-
-
-
-
-10
-19
-43
24
19
11
24
13
-1
1.6 V/ns
2
1.6 V/ns
-
-
-
-
-
-
-
-
-30
-59
-30
-59
24
10
24
10
-7
-7
-
-
-
-
-
-
-
-
-24
-31
-74
31
25
23
14
11
-7
2
-
-
-
-
-
-
-
-
1.4V/ns
1.4V/ns
-18
-47
-89
-18
-47
-89
22
22
5
5
-
-
-
-
-
-
-
-
-127
-12
-52
-19
-62
35
26
14
23
5
-
-
-
-
-
-
-
-
1.2V/ns
1.2V/ns
-140
-140
-35
-77
-35
-77
17
17
-6
-6
-
-
-
-
-
-
-
-
DDR2 SDRAM
Rev. 1.8 July 2007
-115
-40
-50
38
26
17
-7
0
-
-
-
-
-
-
-
-
-
-
1.0V/ns
1.0V/ns
-128
-128
-23
-65
-23
-65
6
6
-
-
-
-
-
-
-
-
-
-
-103
-28
-38
38
12
5
-
-
-
-
-
-
0.8V/ns
-
-
-
-
-
-
0.8V/ns
-116
-116
-11
-53
-53
-11
-
-
-
-
-
-
-
-
-
-
-
-