mt18htf25672az Micron Semiconductor Products, mt18htf25672az Datasheet - Page 11

• Manufacturer Part Number: mt18htf25672az
• Description: 2gb, 4gb X72, Dr, Ecc 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 11:
PDF: 09005aef83c6d17f/Source: 09005aef83c6d1c0
HTF18C256_512x72AZ.fm - Rev. A 9/09 EN
Parameter/Condition
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
(I
bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
(I
HIGH between valid commands; Address bus inputs are stable during
DESELECTs; Data bus inputs are switching
RCD =
CK =
RP =
DD
DD
DD
),
),
),
t
t
t
t
t
RP (I
RAS =
RP =
RC =
CK (I
DD
OUT
OUT
t
RCD (I
DD
),
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
t
t
t
), AL = 0;
RP =
RP (I
RC (I
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
t
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address
),
t
t
Notes: 1. Value calculated as one module rank in this operating condition and all other module
CK =
RRD =
DD
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
Specifications and Conditions – 2GB
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
t
CK (I
t
2. Value calculated reflects all module ranks in this operating condition.
RRD (I
t
CK (I
ranks in I
DD
DD
),
DD
DD
t
DD
CK =
t
), AL = 0;
RC =
), AL =
),
); REFRESH command at every
t
RCD =
DD2P
t
CK (I
t
RC (I
t
RCD (I
t
(CKE LOW).
DD
t
2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
CK =
RCD (I
DD
),
t
DD4W
),
CK =
t
DD
t
RAS =
t
t
CK =
t
RAS =
CK (I
CK =
) - 1 ×
DD
t
); CKE is HIGH, S# is
CK (I
DD
t
t
OUT
CK (I
CK =
t
t
t
CK (I
RAS MAX (I
t
CK =
11
RAS MIN (I
),
t
CK (I
DD
t
= 0mA; BL = 4,
RAS =
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
),
DD
CK (I
t
),
DD
CK (I
t
); CKE is
RAS =
t
RC =
);
DD
t
t
RFC (I
RAS MAX
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
CK =
DD
DD
); CKE is
t
); CKE
t
),
),
RAS
RC
DD
t
CK
)
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
DD7
1
1
2
2
1
2
2
2
2
1
2
1
Electrical Specifications
-1GA
1096
1120
1736
1736
4240
3456
976
112
960
960
800
160
112
©2009 Micron Technology, Inc. All rights reserved.
-80E/
-800
1336
1336
3760
2736
776
936
112
800
800
640
160
960
112
1136
1136
3440
2296
-667
736
856
112
640
640
480
160
880
112
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA