mt18htf25672az Micron Semiconductor Products, mt18htf25672az Datasheet - Page 8

• Manufacturer Part Number: mt18htf25672az
• Description: 2gb, 4gb X72, Dr, Ecc 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

General Description
Serial Presence-Detect Operation
PDF: 09005aef83c6d17f/Source: 09005aef83c6d1c0
HTF18C256_512x72AZ.fm - Rev. A 9/09 EN
The MT18HTF25672AZ and MT18HTF51272AZ DDR2 SDRAM modules are high-speed,
CMOS, dynamic random-access 2GB and 4GB memory modules organized in x72 con-
figurations. These DDR2 SDRAM modules use internally configured 8-bank (1Gb, 2Gb)
DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to Vss, permanently disabling hardware write protection.
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2009 Micron Technology, Inc. All rights reserved.