mt18htf25672az Micron Semiconductor Products, mt18htf25672az Datasheet - Page 12

• Manufacturer Part Number: mt18htf25672az
• Description: 2gb, 4gb X72, Dr, Ecc 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 12:
PDF: 09005aef83c6d17f/Source: 09005aef83c6d1c0
HTF18C256_512x72AZ.fm - Rev. A 9/09 EN
Parameter/Condition
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
(I
stable; Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are
switching
OUT
OUT
RAS =
RP =
RC =
DD
DD
DD
), AL = 0;
); CKE is LOW; Other control and address bus inputs are
),
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RP =
RC (I
t
RAS MIN (I
DD
DD
t
RP (I
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the
2Gb (256 Meg x 8) component data sheet
CK =
t
RRD =
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
), AL = 0;
t
CK (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
Notes: 1. Value calculated as one module rank in this operating condition and all other module
DD
t
RRD (I
DD
DD4W
t
CK =
Specifications and Conditions – 4GB
),
t
DD
t
DD
CK =
2. Value calculated reflects all module ranks in this operating condition.
DD
RC =
t
), AL =
CK (I
), AL = 0;
),
ranks in I
t
t
RCD =
t
CK (I
RC (I
DD
t
); REFRESH command at every
RCD (I
DD
DD
t
t
DD2P
CK =
RCD (I
),
),
t
t
DD
RAS =
RAS =
(CKE LOW).
t
2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
) - 1 ×
CK (I
DD
t
); CKE is HIGH, S# is HIGH between
CK =
t
t
t
RAS MIN (I
RAS MAX (I
t
DD
CK =
CK =
t
CK (I
),
t
CK =
t
CK (I
t
t
RAS =
t
OUT
t
CK =
CK (I
CK (I
DD
t
CK =
12
t
DD
);
CK
= 0mA; BL = 4, CL = CL
DD
DD
t
DD
DD
t
),
t
CK (I
CK =
RAS MAX (I
t
),
),
CK (I
t
); CKE is HIGH, S# is
),
RAS =
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
RCD =
t
RC =
DD
RP =
t
t
RFC (I
CK (I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
); CKE is LOW;
t
); CKE is
t
RAS MAX
t
RC (I
t
RP (I
DD
RCD (I
DD
DD
),
)
DD
),
DD
),
DD
);
);
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
I
Electrical Specifications
DD2P
DD3P
DD0
DD1
DD5
DD6
DD7
1
1
2
2
1
2
2
2
2
1
2
1
©2009 Micron Technology, Inc. All rights reserved.
-80E/-
1000
1400
1040
1120
1040
1520
1600
4800
3200
800
160
720
224
160
-667
1240
1280
1440
4480
2800
880
160
880
960
640
224
880
160
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA