mt18vddt12872phg-335 Micron Semiconductor Products, mt18vddt12872phg-335 Datasheet - Page 19

• Manufacturer Part Number: mt18vddt12872phg-335
• Description: 1gb X72, Ecc, Pll 200-pin Ddr Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
42. CKE must be active (high) during the entire time a
43. I
44. Whenever the operating frequency is altered, not
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
REF later.
DD
DD
2N specifies the DQ, DQS, and DM to be
2F is “worst case.”
DD
DD
2F, I
2F except I
DD
2N, and I
DD
DD
2Q specifies the
2Q are similar,
DD
2Q is
19
45. Leakage number reflects the worst case leakage
46. When an input signal is HIGH or LOW, it is
47. This is the DC voltage supplied at the DDR
200-PIN DDR SDRAM SODIMM
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
SDRAM device and is inclusive of all noise up to
20 MHz. Any noise above 20 MHz at the DDR
SDRAM device generated from any source other
than the device itself may not exceed the DC volt-
age range of +2.5V ±0.2V.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1GB (x72, ECC, PLL)
©2004 Micron Technology, Inc. All rights reserved.