mt18vddt12872phg-335 Micron Semiconductor Products, mt18vddt12872phg-335 Datasheet - Page 8

• Manufacturer Part Number: mt18vddt12872phg-335
• Description: 1gb X72, Ecc, Pll 200-pin Ddr Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
specifies the type of burst (sequential or interleaved),
A4–A6 specify the CAS latency, and A7–A12 specify the
operating mode.
Burst Length
burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
ation or incompatibility with future versions may result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see note 5 of Table 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both read and write bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
Mode register bits A0–A2 specify the burst length, A3
Read and write accesses to the DDR SDRAM are
Reserved states should not be used, as unknown oper-
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
8
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram, on page 9.
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
The READ latency is the delay, in clock cycles,
Figure 4: Mode Register Definition
0*
14
BA1
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
13
BA0
12
A12 A11
Operating Mode
11
10
A10
M12 M11
0
0
-
9
A9
0
0
-
8
A8
M10
0
0
-
1GB (x72, ECC, PLL)
Diagram
7
A7 A6 A5 A4 A3
M9
M6
0
0
CAS Latency BT
-
0
0
0
0
1
1
1
1
6
M8 M7
M5
0
1
-
0
0
1
1
0
0
1
1
5
0
0
-
M4
©2004 Micron Technology, Inc. All rights reserved.
0
1
0
1
0
1
0
1
4
M6-M0
M3
0
1
Valid
Valid
3
-
Burst Length
M2
2
0
0
0
0
1
1
1
1
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
2.5
2
3
M0
0
1
0
1
0
1
0
1
0
Interleaved
Burst Type
Sequential
Burst Length
Mode Register (Mx)
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 0
Address Bus
2
4
8