mt18vddt12872phg-335 Micron Semiconductor Products, mt18vddt12872phg-335 Datasheet - Page 9

• Manufacturer Part Number: mt18vddt12872phg-335
• Description: 1gb X72, Ecc, Pll 200-pin Ddr Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Table 6:
NOTE:
Table 7:
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
1. For a burst length of two, A1–Ai select the two- data-
2. For a burst length of four, A2–Ai select the four- data-
3. For a burst length of eight, A3–Ai select the eight-
4. Whenever a boundary of the block is reached within a
5. ii = 9, 11
LENGTH
SPEED
BURST
element block; A0 selects the first access within the
block.
element block; A0–A1 select the first access within the
block.
data-element block; A0–A2 select the first access within
the block.
given sequence above, the following access wraps
within the block.
-26A
-335
-262
-265
2
4
8
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
75
75
75
75
0
0
1
1
0
0
1
1
0
0
1
1
CL = 2
CLOCK FREQUENCY (MHZ)
A0
ALLOWABLE OPERATING
f
f
f
f
0
1
0
1
0
1
0
1
0
1
0
1
0
1
133
133
133
100
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
ORDER OF ACCESSES WITHIN
SEQUENTIAL
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
A BURST
75
75
75
75
CL = 2.5
INTERLEAVED
f
f
f
f
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
167
133
133
133
9
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
operation or incompatibility with future versions may
result.
Operating Mode
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues.
TER SET command with bits A7 and and A9–A12 each
set to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
COMMAND
COMMAND
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by issuing a
A DLL reset is initiated by issuing a MODE REGIS-
200-PIN DDR SDRAM SODIMM
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
1GB (x72, ECC, PLL)
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n