mt18vddt12872phg-335 Micron Semiconductor Products, mt18vddt12872phg-335 Datasheet - Page 4

• Manufacturer Part Number: mt18vddt12872phg-335
• Description: 1gb X72, Ecc, Pll 200-pin Ddr Sdram Sodimm
• Manufacturer: Micron Semiconductor Products

Table 5:
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
71, 72, 73, 74, 79, 80, 83,
106, 107, 108, 109, 110,
11, 25, 47, 61, 77, 133,
12, 26, 48, 62, 78, 134,
99, 100, 101,102, 105,
PIN NUMBERS
118, 119, 120
111, 112, 115
148, 170, 184
147,169, 183
121, 122
117, 116
35, 37
95, 96
84
Pin Descriptions
WE#, CAS#, RAS#
DQS0–DQS8
CKE0, CKE1
DM0–DM8
CK0, CK0#
SYMBOL
BA0, BA1
CB0–CB7
S0#, S1#
A0–A12
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK and CK# are differential clock inputs distributed
through an on-board PLL to all devices. All address and control
input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQ and DQS) is
referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers.and output drivers. Taking CKE
LOW provides PRECHARGE POWER- DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All com- mands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: A0–A12 provide the row address for ACTIVE
commands, and the column address, and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Check Bits.
4
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
1GB (x72, ECC, PLL)
©2004 Micron Technology, Inc. All rights reserved.
DD
is applied and until