m470l1624bt0 Samsung Semiconductor, Inc., m470l1624bt0 Datasheet - Page 6

• Manufacturer Part Number: m470l1624bt0
• Description: 128mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM SPEC Items and Test Conditions
M470L1624BT0
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); Vin = Vref for DQ,DQS and DM
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min);
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax;
DQ, DQS and DM inputs changing twice per clock cycle;
address and other control inputs changing once per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
50% of data changing at every burst; lout = 0 m A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz ; distributed refresh
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
Orerating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
Vin = Vref for DQ ,DQS and DM
200pin DDR SDRAM SODIMM
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Symbol
Rev. 0.2 Dec. 2001