m470l1624bt0 Samsung Semiconductor, Inc., m470l1624bt0 Datasheet - Page 7

• Manufacturer Part Number: m470l1624bt0
• Description: 128mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
2. Timing patterns
I
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
2. Timing patterns
DD7A
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
DDR SDRAM I
M470L1624BT0
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK,Read with autoprecharge
* Module
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
changing. lout = 0mA
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
IDD6
: Operating current: Four bank operation
Symbol
IDD4W
IDD2Q
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD7A
IDD0
IDD1
IDD5
I
DD
Low power
Normal
was calculated on the basis of component
DD
spec table
A2(DDR266@CL=2)
1040
1260
1720
480
660
128
220
180
200
280
900
12
6
B0(DDR266@CL=2.5)
I
DD
1040
1260
1720
480
660
128
220
180
200
280
900
12
and can be differently measured according to DQ loading cap.
6
200pin DDR SDRAM SODIMM
A0(DDR200@CL=2)
1000
1520
440
600
100
180
140
160
220
880
820
12
6
Rev. 0.2 Dec. 2001
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Optional
Notes