m391b5273bh1 Samsung Semiconductor, Inc., m391b5273bh1 Datasheet - Page 26
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m391b5273bh1
Manufacturer Part Number
m391b5273bh1
Description
Ddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M391B5273BH1.pdf
(33 pages)
DDR3-1600 Speed Bins
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
Supported CL Settings
Supported CWL Settings
Unbuffered DIMM
Parameter
CL-nRCD-nRP
Speed
CWL = 5,6,7
CWL = 7, 8
CWL = 5,6
CWL = 5,6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 7
CWL = 8
CWL = 7
CWL = 8
CWL = 8
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Symbol
tRCD
tRAS
tRP
tRC
tAA
26 of 33
(13.125)
(13.125)
(13.125)
(48.125)
13.75
13.75
13.75
48.75
1.875
1.875
1.25
min
2.5
1.5
1.5
35
5,9
5,9
5,9
5,9
(Optional) Note 9,10
(Optional) Note 9,10
(Optional) Note 5,9
6,7,8,9,10,11
DDR3-1600
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11-11-11
5,6,7,8
TBD
9*tREFI
<1.875
<1.875
max
<2.5
<2.5
<1.5
3.3
20
-
-
-
Rev. 1.0 December 2008
DDR3 SDRAM
Units
nCK
nCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,8
1,2,3,4,8
1,2,3,4,8
1,2,3,4,8
1,2,3,4,8
1,2,3,8
1,2,3,8
1,2,3,4
1,2,3,4
1,2,3,8
1,2,3,4
1,2,3,5
Note
4
4
4
4
4
4
4