m391b5273bh1 Samsung Semiconductor, Inc., m391b5273bh1 Datasheet - Page 30

• Manufacturer Part Number: m391b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Percharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WR command to Power Down entry
(BL4MRS)
Timing of WRA command to Power Down entry
(BL4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT high time without write command or with wirte
command and BC4
ODT high time with Write command and BL8
Asynchronous RTT tum-on delay (Power-Down with
DLL frozen)
Asynchronous RTT tum-off delay (Power-Down with
DLL frozen)
ODT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
RTT dynamic change skew
First DQS pulse rising edge after tDQSS margining
mode is programmed
DQS/DQS delay after tDQS margining mode is pro-
grammed
Setup time for tDQSS latch
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
Write leveling output delay
Write leveling output error
Unbuffered DIMM
ODT Timing
Write Leveling Timing
Parameter
Speed
tWRAPDEN
tWRAPDEN
tMRSPDEN
tWLDQSEN
tACTPDEN
tREFPDEN
tWRPDEN
tWRPDEN
tRDPDEN
tPRPDEN
tWLMRD
tCPDED
tAONPD
tAOFPD
Symbol
tXPDLL
ODTH4
ODTH8
tWLOE
tWLH
tWLO
tCKE
tAON
tAOF
tADC
tWLS
tPD
tXP
WL + 4 +WR +1
WL +2 +WR +1
WL + 4 +(tWR/
WL + 2 +(tWR/
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
5.625ns)
(10nCK,
(3nCK,
(3nCK,
7.5ns)
24ns)
max
max
max
-300
MIN
245
245
0.3
0.3
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1066
30 of 33
9*tREFI
MAX
300
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL + 4 +WR +1
WL +2 +WR +1
WL + 4 +(tWR/
WL + 2 +(tWR/
(3nCK,6ns)
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
5.625ns)
(10nCK,
(3nCK,
24ns)
MIN
max
max
max
-250
195
195
0.3
0.3
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1333
9*tREFI
MAX
250
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 1.0 December 2008
WL + 4 +WR +1
WL +2 +WR +1
WL + 4 +(tWR/
WL + 2 +(tWR/
(3nCK,6ns)
(3nCK,5ns)
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
(10nCK,
24ns)
-225
MIN
max
max
max
165
165
0.3
0.3
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1600
DDR3 SDRAM
9*tREFI
MAX
225
8.5
8.5
0.7
0.7
7.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tCK
tCK
tCK
ns
ns
ps
ps
ps
ns
ns
20,21
Note
15
20
20
10
10
7,f
8,f
2
9
9
3
3
f