m391b5273bh1 Samsung Semiconductor, Inc., m391b5273bh1 Datasheet - Page 4

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m391b5273bh1

Manufacturer Part Number
m391b5273bh1
Description
Ddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.0 DDR3 Unbuffered DIMM Ordering Information
Note :
- "##" - F8/H9/K0
- F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 & K0 - 1600Mbps 11-11-11
2.0 Key Features
3.0 Address Configuration
Unbuffered DIMM
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
• 533MHz f
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 6(DDR3-1066) and 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
• Asynchronous Reset
CAS Latency
write [either On the fly using A12 or MRS]
tRCD(min)
tRAS(min)
tCK(min)
tRP(min)
tRC(min)
DDQ
Speed
M378B5273BH1-CF8/H9/K0
M391B5273BH1-CF8/H9/K0
256x8(2Gb) based Module
= 1.5V ± 0.075V
Part Number
CK
Organization
for 1066Mb/sec/pin, 667MHz f
DDR3-1066
13.125
13.125
50.625
1.875
7-7-7
37.5
7
Density
CK
4GB
4GB
Row Address
CASE
for 1333Mb/sec/pin
A0-A14
85°C, 3.9us at 85°C < T
Organization
512Mx64
512Mx72
4 of 33
DDR3-1333
Column Address
9-9-9
13.5
13.5
49.5
1.5
36
9
CASE
A0-A9
256Mx8(K4B2G0846B-HC##)*16
256Mx8(K4B2G0846B-HC##)*18
Component Composition
≤ 95°C
Bank Address
BA0-BA2
Rev. 1.0 December 2008
DDR3-1600
11-11-11
13.75
13.75
48.75
1.25
11
35
DDR3 SDRAM
Number of
Rank
Auto Precharge
2
2
A10/AP
Unit
tCK
Height
ns
ns
ns
ns
ns
30mm
30mm

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