mt9v034c12stmdes aptina, mt9v034c12stmdes Datasheet - Page 40

• Manufacturer Part Number: mt9v034c12stmdes
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Table 9:
PDF: 09005aef8366edcb/Source: 09005aef8366ede5
MT9V034_DS - Rev. A 10/08 EN
0xB3 (179) LVDS Data Control
0xB4 (180) LVDS Latency
0xB5 (181) LVDS Internal Sync
0xB6 (182) LVDS Payload Control
0xB7 (183) Stereoscopy Error Control
0xB8 (184) Stereoscopy Error Flag
0xB9 (185) LVDS Data Output
0xBA (186) AGC Gain Output
0xBB (187) AEC Exposure Output
15:0
15:0
2:0
2:0
1:0
6:0
Bit
4
4
0
0
0
1
2
0
Shift-clk Delay
Element Select
LVDS Clock
Output Enable
Data Delay
Element Select
LVDS Data Input
Enable
Stream Latency
Select
LVDS Internal
Sync Enable
Use 10-bit Pixel
Enable
Enable Stereo
Error Detect
Enable Stick
Stereo Error Flag
Clear Stereo Error
Flag
Stereoscopy Error
Flag
Combo Reg
AGC Gain
AEC Exposure
Bit Name
Register Descriptions (continued)
The amount of shift-CLK delay that minimizes inter-
sensor skew.
When set, the LVDS clock (SHFT_CLKOUT) pins are
disabled. Has no effect on SER_DATAOUT pins.
The amount of data delay that minimizes inter-
sensor skew.
When set, the LVDS Data Receiver (SER_DATAIN) pins
are disabled. If this bit is changed, it is mandatory
that a soft reset (R0x0C) is then issued for proper
operation.
The amount of delay so that the two streams are in
sync.
When set, the MT9V034 generates sync pattern (data
with all zeros except start bit) on
LVDS_SER_DATA_OUT.
When set, all 10 bits will contain pixel (with
embedded controls) in standalone mode. If clear,
payload will be 8 bits of pixel with 2 bits of controls.
Set this bit to enable stereo error detect mechanism.
When set, the stereo error flag remains asserted
once an error is detected unless clear stereo error flag
(bit 2) is set.
Set this bit to clear the stereoscopy error flag (R0xB8
returns to logic 0).
Stereoscopy error status flag. It is also directly
connected to the ERROR output pin.
This 16-bit value contains both 8-bit pixel values
from both stereoscopic master and slave sensors. It
can be used in diagnosis to determine how well in
sync the two sensors are. Captures the state when
master sensor has issued a reserved byte and slave
has not.
Note: This register should be read from the
stereoscopic master sensor only.
Status register to report the current gain value
obtained from the AGC algorithm.
Status register to report the current exposure value
obtained from the AEC algorithm.
Bit Description
Aptina Confidential and Proprietary
40
MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor
Default in
Hex (Dec)
00C8
(200)
10
Aptina Imaging reserves the right to change products or specifications without notice.
0
0
1
0
1
0
0
0
0
0
Shadowed
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
©2008 Aptina Imaging Corporation. All rights reserved.
Values
Legal
(Dec)
0–7
0–7
0–3
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
Registers
Read/
Write
W
W
W
W
W
W
W
W
W
W
R
R
R
R