saa5284 NXP Semiconductors, saa5284 Datasheet - Page 14

• Manufacturer Part Number: saa5284
• Description: Multimedia Video Data Acquisition Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 5 Intel-mode interface DMA cycle timing (12 MHz clock)
Note
1. This timing will be up to 3 clock cycles for the first read in DMA transfer.
1998 Feb 05
handbook, full pagewidth
SYMBOL
Multimedia video data acquisition circuit
(1) Read data pipelined, so no RD LOW to data valid set-up time.
t
t
t
t
t
t
t
1
2
3
4
5
6
7
(same signal
as DMACK)
DMARQ to DMACK
RD LOW to DMARQ LOW
cycle time
DMACK to RD active
data set-up time
data hold time
data hold from DMACK HIGH
D7 to D0
DMARQ
DMACK
RD
CS
(1)
t 1
t 4
Fig.5 Intel mode interface DMA cycle timing.
DESCRIPTION
valid data
t 5
t 3
14
t 7
t 6
valid data
t 2
0
0
252
0
83
0
MIN.
212
0
90
83
(1)
Objective specification
MAX.
SAA5284
MGK147
UNIT
ns
ns
ns
ns
ns
ns
ns