saa5284 NXP Semiconductors, saa5284 Datasheet - Page 7

• Manufacturer Part Number: saa5284
• Description: Multimedia Video Data Acquisition Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8
8.1
There are three separate +5 V (V
1. V
2. V
3. V
8.2
The master frequency reference for the IC is a
12, 13.5, 15 or 16 MHz crystal oscillator. The tolerance on
the clock frequency is 500
specifications of the crystal are given in Table 2.
If preferred, an external 12, 13.5, 15 or 16 MHz ( 1.5 kHz)
frequency source may be connected to OSCIN instead of
the crystal.
8.3
The RESET pin should be held HIGH for a minimum of two
clock cycles. The reset signal is passed through a Schmitt
trigger internally.
Direct addressed registers (i.e. those addressed using the
A0 to A2 pins) are set to 00H after power-up. All other
register bits are assumed to be in random states after
power-up.
8.4
Register bit selection between two video sources.
8.5
This section comprises a line and field sync separator, a
video clamp, an ADC and a custom adaptive digital filter
with DPLL based timing circuit.
Table 2 Crystal characteristics
1998 Feb 05
SYMBOL
Multimedia video data acquisition circuit
front-end sections: ADC and sync separator, to reduce
interference from the rest of the front-end
current
FUNCTIONAL DESCRIPTION
DDA
DDX
DDD
C1
C2
X
X
R
X
Power supply strategy
Clocking strategy
Power-on reset
Analog switch
Analog video-to-data byte converter
a
d
r
j
supplies the critical noise-sensitive analog
supplies all sections which take standing DC
supplies the rest of the logic.
series capacitance
parallel capacitance
resonant resistance
ageing
adjustment tolerance
drift
10
6
DD
(1.5 kHz). Further
) connections to the IC:
PARAMETER
7
The analog video-to-data byte converter is specifically
designed to overcome the most commonly found types of
distortion of a broadcast video signal. It is also fully
multi-standard. The data type to be demodulated is
programmable on a line-by-line basis using 4 register bits
per line for lines 2 to 23 (PAL numbering),
fields 1 and 2, and 4 further bits for all lines combined.
8.6
If using a slow (e.g. 80C51) microcontroller, it is necessary
to reduce the amount of data acquired by SAA5284 before
downloading to the microcontroller to avoid it being
swamped by unwanted data. Packet filtering is available
for this purpose. A common use of this would be to acquire
only packet 8/30 in 625-line WST. The packet filter
includes optional (8, 4) Hamming correction.
8.7
This is a 2 kbyte RAM which acts as a buffer for storing
received packets. The first 44 bytes are reserved for
control information. The rest of the RAM is divided into
44-byte rows (or packets), each holding the data received
on one incoming CVBS line. In the case of a WST packet
received, the data stored consists of a Magazine and
Row-Address Group (2 bytes), followed by the 40 bytes of
packet data. When data in other formats than WST is
received, this is stored in the packet buffer in the same
way. In each case, the data is preceded by two information
bytes which record on which line and field the packet was
received, and what the data type is.
8.8
FIFO hardware is provided to manage the ‘read’ address
for the host processor, i.e. data is read repeatedly from the
same 8-bit port, and appears byte-serially in the order of
reception. The read address can be reset to the start of the
packet buffer (the first 44-byte packet), back to the start of
the current packet, or incremented to the start of the next
packet.
Packet filtering
Packet buffer
FIFO
MIN.
18.5
4.9
TYP.
Objective specification
50
5
25
25
MAX.
10
SAA5284
10
10
6
6
6
fF
pF
per year
UNIT