saa5284 NXP Semiconductors, saa5284 Datasheet - Page 8

• Manufacturer Part Number: saa5284
• Description: Multimedia Video Data Acquisition Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.9
The SAA5284 has a multi-standard 8-bit I/O interface.
To reduce the amount of host I/O space used, the parallel
interface has only 3 address inputs (A0, A1 and A2).
An extended addressing (pointer) scheme and the data
FIFO are used to allow access to the full set of SAA5284
registers and the full span of the packet buffer.
As well as the 8 data I/O lines and 3 address lines, there
are the following control signals: RD (read LOW), WR
(write LOW), CS0 (chip select LOW), CS1(second chip
select LOW), INT (interrupt request), DMARQ (DMA
request), DMACK (DMA acknowledge) and RDY (ready).
In order to maintain compatibility with Motorola and Intel
type buses, two control signals SEL0 and SEL1 are
provided to configure the host interface. These signals
allow configuration of the host interface to work with the
Motorola or Intel style interfaces.
The host interface has a digital video mode. Digital video
mode may be used to allow the SAA5284 to pass decoded
VBI data into a system using the digital video bus.
9
In accordance with the Absolute Maximum Rating System (IEC 134).
10 QUALITY & RELIABILITY
In accordance with “SNW-FQ-611-E” .
1998 Feb 05
V
V
V
I
I
T
T
IOK
O(max)
V
stg
amb
DD
I(max)
O(max)
Multimedia video data acquisition circuit
DDD DDA DDX
SYMBOL
LIMITING VALUES
Host interface
supply voltage (all supplies)
input voltage (any input)
output voltage (any output)
supply voltage difference between V
DC input or output diode current
output current (any output)
storage temperature
operating ambient temperature
PARAMETER
DDD
, V
8
8.10
The host interface provides comprehensive support for
interrupt generation. The interrupt may be programmed to
occur when a particular number of packets of VBI data are
available in the cache RAM. The interrupts can be further
controlled to occur on a specific line in the TV frame.
The interrupts can also be self masking if required.
8.11
Burst and demand mode DMA are supported. In burst
mode, the number of packets to transfer can be defined.
An interrupt can be generated when DMA is finished. This
can be self masking.
8.12
The I
transmitter at up to 400 kHz. The I
selectable as 20H or 22H. All functionality is available
using the I
speed. It is possible to use the I
DDA
and V
2
C-bus interface functions as a slave receiver or
Interrupt support
DMA support
I
2
C-bus interface
DDX
2
C-bus although with a slower data transfer
0.3
0.3
0.3
55
20
MIN.
2
+6.5
V
V
0.25
20
10
+125
+70
C-bus in all modes.
DD
DD
2
MAX.
Objective specification
C-bus address is
+ 0.5
+ 0.5
SAA5284
V
V
V
V
mA
mA
C
C
UNIT