ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 15

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ppc440spe

Manufacturer Part Number
ppc440spe
Description
Powerpc 440spe Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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PowerPC 440SPe Embedded Processor
General Purpose Timers (GPT)
Provides a time base counter and system timers additional to those defined in the processor core.
General Purpose IO (GPIO) Controller
Universal Interrupt Controller (UIC)
Four cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
JTAG
Features include:
AMCC Proprietary
• 32-bit time base counter driven by the OPB bus clock
• Seven 32-bit compare timers
• Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB
• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
• Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).
• 16 external interrupts
• 101 internal interrupts
• Edge-triggered or level-sensitive
• Positive- or negative-active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
bus master accesses.
capabilities acts as a GPIO or is used for another purpose.
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
15

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