ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 77

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
Initialization
The PPC440SPe provides the option for setting initial parameters based on default values or by reading them from
a serial “bootstrap” ROM attached to the IIC0 bus. These options are defined by strapping on three external pins
(see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440SPe start-up. The actual capture instant is the nearest SysClk edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Serial Bootstrap ROM
During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In
this case, at the de-assertion of SysReset, the PPC440SPe sequentially reads up to 32 bytes from the ROM device
on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly.
The initialization settings and their default values are covered in detail in the PPC440SPe Embedded Processor
User’s Manual.
AMCC Proprietary
Table 21. Strapping Pin Assignments
Serial Bootstrap ROM is disabled (Bit 0 off).
Refer to the IIC Bootstrap Controller chapter in the
PPC440SPe Embedded Processor User’s Manual
for details.
Serial Bootstrap ROM is enabled (Bit 0 on).
The options being selected are the IIC0 slave
address that responds with strapping data and
reading 128 bits from the Bootstrap ROM.
Serial Bootstrap ROM is enabled (Bit 0 on).
The options being selected are the IIC0 slave
address that responds with strapping data and
reading 256 bits from the Bootstrap ROM.
Function
Boot from EBC
Boot from PCI
Option
0x54
0x50
0x54
0x50
(UART0_DCD)
Bit 0
H13
0
0
1
1
1
1
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
Pin Strapping
(UART0_DSR)
Bit 1
C12
0
1
0
1
0
1
(UART0_CTS)
Bit2
B08
0
0
1
1
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