ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 63

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ppc440spe

Manufacturer Part Number
ppc440spe
Description
Powerpc 440spe Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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PowerPC 440SPe Embedded Processor
Figure 4. Clock Timing Waveform
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SPe. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440SPe the following conditions must be met:
AMCC Proprietary
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
• The maximum frequency deviation cannot exceed -1%, and the modulation frequency cannot exceed 40kHz.
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
• Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Table 12. Clocking Specifications
PPC440SPe with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
In some cases, on-board PPC440SPe peripherals impose more stringent requirements.
modulation.
Processor Clock (CPU Clock)
MemClkOut
OPB Clock and PerClk
MAL Clock
Symbol
T
F
T
F
T
F
T
F
T
CH
C
C
C
C
C
C
C
C
Frequency
Period
Frequency
Period
High time
Frequency
Period
Frequency
Period
Parameter
T
CH
T
C
45% of nominal period
Min
400
200
1.5
12
45
12
3
T
CL
Preliminary Data Sheet
55% of nominal period
Revision 1.23 - Sept 21, 2006
666.66
333.33
83.33
83.33
Max
22.2
2.5
5
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
63

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