ppc460ex Applied Micro Circuits Corporation (AMCC), ppc460ex Datasheet
ppc460ex
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ppc460ex Summary of contents
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... JTAG interface for board level testing • Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface • Optional security feature (PPC460EX-S) with KASUMI • Available in RoHS compliant, lead-free package Technology: CMOS Cu-08, 90nm. Package: 35mm, 728-ball thermally and electrically enhanced plastic ball grid array (TE-EPBGA) ...
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... PPC460EX Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Floating Point Unit (FPU Cache/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Security Function (optional PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PCI Express Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External Peripheral Bus Controller (EBC Ethernet Controller ...
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... Revision 1.12 – July 17, 2008 Preliminary Data Sheet Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC460EX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 35mm, 728-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 7. Input Setup and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 8 ...
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... PPC460EX Embedded Processor Ordering and PVR Information For information on the availability of the following parts, contact your local AMCC sales office. For additional information on the part number structure see Figure 1. Order Part Number Product Name (see Notes) PPC460EX PPC460EX-SpAfff(f)T PPC460EX ...
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... PCI-E0 Int PCI-E1 (x1) Hand (x4) 1 lane 4 lanes HSS x1 HSS x1/ Slave Master n The PPC460EX is a system on a chip (SOC). AMCC Proprietary 460EX – PPC460EX Embedded Processor DCRs IIC(x2) UART x4 BSC DCR Bus On-chip Peripheral Bus (OPB)–32 bits, 100MHz DMA SRAM ...
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... PPC460EX Embedded Processor Address Maps The PPC460EX incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC460EX processor through the use of mtdcr and mfdcr instructions ...
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... Boot ROM EBC Memory Bank 0 Internal PLB Interfaces (LL) Reserved Local Memory Alias (HB) Aliased DDR SDRAM AMCC Proprietary 460EX – PPC460EX Embedded Processor Sub Function Start Address 6 0000 0004 C000 0000 0000 0004 E800 0000 0000 0004 EF60 0000 0000 0004 EF60 0200 ...
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... PPC460EX Embedded Processor Table 1. System Memory Address Map (Part Function PCI Express Memory PCI I/O PC Express Memory PCI Extra I/O PCI Express Memory PCI Configuration Registers Reserved PCI/PCIE Space (HB) PCI Local Registers Reserved PCI Special Cycle Reserved PCI Express Interrupt Handler ...
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... DMA Controller Reserved Notes: 1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 B). AMCC Proprietary 460EX – PPC460EX Embedded Processor Base Address Start Address 000 000 00 0000 110x ...
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... Single-cycle throughput on most instructions • Thirty-two 64-bit floating point registers L2 Cache/SRAM The PPC460EX also provides a 256KB L2 cache between the Processor Local Bus and the processor’s D- and I-caches. This memory unit can be alternatively programmed to function as 256KB of SRAM. Features include: • Four banks of 64KB each • ...
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... Full LRU replacement algorithm – Write through, look aside On-Chip Memory (OCM) The PPC460EX provides 64KB of on-chip memory. Features include: • 128-bit bus width • 128-bit slave attachment, addressable by any PLB master • Transfers by PLB slave cycles: – ...
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... DCR – 32-bit data path – 10-bit address Security Function (optional) The built-in security function (PPC460EX-S only cryptographic engine attached to the PLB with built-in DMA and interrupt controllers. Features include: • Federal Information Processing Standard (FIPS) 140-2 design • Support for an unlimited number of Security Associations (SA) • ...
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... Compliant with PCI Express base specification 1.1 • Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream) – Applications compliant with MSI rules are limited to one Endpoint port per PPC460EX • Power Management • Supports one virtual channel (VC0) no Traffic Class (TC) filtering • ...
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... PPC460EX Embedded Processor • Buffering in each PCI Express port for the following transaction types: – 2KB Replay buffer flight transactions – 2KB (x4) or 1KB (x1) for Outbound posted Writes – 2KB (x4) or 1KB (x1) for Outbound Reads completion – 2KB (x4) or 1KB (x1) for Inbound posted Writes – ...
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... Checksum generation for TCP/UDP/IP headers in the transmit path • TCP segmentation support in the transmit path • IPv4 and IPv6 support • IPv6 header extension support • Wake On LAN handling • 256-bit hash table to filter multicast frames • DMA capability AMCC Proprietary 460EX – PPC460EX Embedded Processor 15 ...
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... PPC460EX Embedded Processor • Interrupt coalescence DMA 4-Channel Controller The 4-channel DMA controller provides a DMA interface between the PLB memories and internal and external peripheral devices. Features include: • Supports the following transfers: – Memory-to-memory – Buffered peripheral to memory – ...
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... One programmable interrupt request signal • Provides full management of all IIC bus protocols • Programmable error recovery • Port 0 includes an integrated BSC that supports a serial Bootstrap ROM with default override parameters at initialization AMCC Proprietary 460EX – PPC460EX Embedded Processor ™ ® ...
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... PPC460EX Embedded Processor Serial Peripheral Controller (SPI/SCP) The Serial Peripheral Interface (also known as the Serial Communications Port full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. ...
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... Sixty-four GPIOs multiplexed with other functions. DCRs control whether a GPIO pin acts as a GPIO or is used for another purpose. • Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). AMCC Proprietary 460EX – PPC460EX Embedded Processor 19 ...
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... PPC460EX Embedded Processor Universal Interrupt Controller (UIC) Universal Interrupt Controllers (UICs) provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) do not use UIC resources. ...
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... AMCC Proprietary 460EX – PPC460EX Embedded Processor Part Number Heat Slug PCB Substrate 0.4 - 0.6 1.0 Notes: 1. All dimensions are in mm. 7 728 x 0.60 ± 0.10 Solder Ball ...
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... PPC460EX Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list— ...
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... ClkEn0 ClkEn1 ClkEn2 ClkEn3 [DMAAck0]GPIO47[PerAddr06][IRQ14] [DMAAck1]GPIO44[PerCS4][IRQ11] [DMAAck2]GPIO31[PerPar1][IRQ8] [DMAAck3]GPIO36[UART0CTS][UART3Rx] [DMAReq0]GPIO46[PerAddr05][IRQ13] [DMAReq1]GPIO43[PerCS3][NFCE3][IRQ10] [DMAReq2]GPIO30[PerPar0][IRQ7] [DMAReq3]GPIO33[PerPar3][IRQ4] AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group L03 L06 M03 M05 N03 N06 P05 T03 U02 Power ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 3 of 26) Signal Name DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 E1OV ...
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... EAVDD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 [EOT0/TC0]GPIO48[PerAddr07][IRQ15] [EOT1/TC1]GPIO45[PerCS5][IRQ12] [EOT2/TC2]GPIO32[PerPar2][IRQ9] [EOT3/TC3]GPIO37[UART0RTS][UART3Tx] ExtReset AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group AP12 Power AP11 AC31 AC30 AE32 AE34 DDR2/1 SDRAM AC34 AC32 AD31 AD30 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 5 of 26) Signal Name GMC0CD, GMC1RxClk, RMII1RxEr GMC0CrS, GMC1TxClk, RMII0CrSDV GMC0GTxClk, GMC0TxClk GMC0RxClk, GMC0RxClk GMC0RxD0, GMC0RxD0, RMII0RxD0, SMII0RxD GMC0RxD1, GMC0RxD1, RMII0RxD1, SMII1RxD GMC0RxD2, GMC0RxD2, RMII1RxD0 GMC0RxD3, GMC0RxD3, RMII1RxD1 GMC0RxD4, GMC1RxD0 GMC0RxD5, GMC1RxD1 ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group A01 A02 A03 A33 A34 B01 B02 B03 B07 B12 B23 B28 B33 B34 C01 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 7 of 26) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group V16 V17 V18 V19 W14 W15 W16 W17 W18 W19 W20 W21 W29 Y15 Y16 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 9 of 26) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group AN01 AN02 AN03 AN07 AN12 AN23 AN28 AN31 AN33 AN34 Power AP01 AP02 AP03 AP04 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 11 of 26) Signal Name GPIO00[USB2HD0] GPIO01[USB2HD1] GPIO02[USB2HD2] GPIO03[USB2HD3] GPIO04[USB2HD4] GPIO05[USB2HD5] GPIO06[USB2HD6] GPIO07[USB2HD7] GPIO08[USB2DD0] GPIO09[USB2DD1] GPIO10[USB2DD2] GPIO11[USB2DD3] GPIO12[USB2DD4] GPIO13[USB2DD5] GPIO14[USB2DD6] GPIO15[USB2DD7] GPIO16[USB2HStop] GPIO17[USB2HNext] GPIO18[USB2HDir] GPIO19[USB2DStop] GPIO20[USB2DNext] GPIO21[USB2DDir] GPIO22[NFRdyBusy] GPIO23[NFREn] GPIO24[NFWEn] GPIO25[NFCLE] GPIO26[NFALE] GPIO27[IRQ0] ...
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... GPIO54[TrcES2] GPIO55[TrcES3] GPIO56[TrcES4] GPIO57[TrcTS0] GPIO58[TrcTS1] GPIO59[TrcTS2] GPIO60[TrcTS3] GPIO61[TrcTS4] GPIO62[TrcTS5] GPIO63[TrcTS6] Halt HISRRst IIC0SClk IIC0SData [IIC1SClk]SPIClkOut [IIC1SData]SPIDO AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group A14 F13 E34 E32 E31 D33 D32 D34 C12 B22 D25 A22 E21 D21 B32 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 13 of 26) Signal Name [IRQ0]GPIO27 [IRQ1]GPIO28 [IRQ2]GPIO29 [IRQ3]GPIO40 [IRQ4]GPIO33[PerPar3][DMAReq3] [IRQ5]GPIO38[UART0DTR][UART1Tx] [IRQ6]GPIO39[UART0RI][UART1Rx] [IRQ7]GPIO30[PerPar0][DMAReq2] [IRQ8]GPIO31[PerPar1][DMAAck2] [IRQ9]GPIO32[PerPar2][EOT2/TC2] [IRQ10]GPIO43[PerCS3][NFCE3][DMAReq1] [IRQ11]GPIO44[PerCS4][DMAAck1] [IRQ12]GPIO45[PerCS5][EOT1/TC1] [IRQ13]GPIO46[PerAddr05][DMAReq0] [IRQ14]GPIO47[PerAddr06][DMAAck0] [IRQ15]GPIO48[PerAddr07][EOT0/TC0] ...
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... MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group P30 N34 R32 R30 N33 N32 P34 R31 R34 T34 V34 T32 R33 T31 U33 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 15 of 26) Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 ...
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... PAV DD PAV DD AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group AJ19 AB29 DDR2/1 SDRAM AJ22 T29 A25 E24 B22 D25 A22 NAND Flash F26 C24 B24 A24 B05 B09 B16 B19 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 17 of 26) Signal Name PCI0AD00 PCI0AD01 PCI0AD02 PCI0AD03 PCI0AD04 PCI0AD05 PCI0AD06 PCI0AD07 PCI0AD08 PCI0AD09 PCI0AD10 PCI0AD11 PCI0AD12 PCI0AD13 PCI0AD14 PCI0AD15 PCI0AD16 PCI0AD17 PCI0AD18 PCI0AD19 PCI0AD20 PCI0AD21 PCI0AD22 PCI0AD23 PCI0AD24 PCI0AD25 PCI0AD26 PCI0AD27 ...
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... PCI0Req1 PCI0Req2 PCI0Req3 PCI0Reset PCI0SErr PCI0Stop PCI0TRdy PCIE0AVReg[SATA0AVReg] PCIE0CalRN[SATA0CalRN] PCIE0CalRP[SATA0CalRP] PCIE0RefClk[SATA0RefClk] PCIE0RefClk[SATA0RefClk] PCIE0Rx0[SATA0Rx0] PCIE0Rx0[SATA0Rx0] PCIE0Tx0[SATA0Tx0] PCIE0Tx0[SATA0Tx0] AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group G03 H04 PCI G01 H03 D01 J04 C04 PCI E09 D07 B06 J06 H02 PCI ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 19 of 26) Signal Name PCIE1AVReg PCIE1CalRN PCIE1CalRP PCIE1RefClk PCIE1RefClk PCIE1Rx0 PCIE1Rx0 PCIE1Rx1 PCIE1Rx1 PCIE1Rx2 PCIE1Rx2 PCIE1Rx3 PCIE1Rx3 PCIE1Tx0 PCIE1Tx0 PCIE1Tx1 PCIE1Tx1 PCIE1Tx2 PCIE1Tx2 PCIE1Tx3 PCIE1Tx3 40 Revision 1.12 – July 17, 2008 Preliminary Data Sheet ...
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... PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0[NFCE0] [PerCS1]GPIO41[NFCE1] [PerCS2]GPIO42[NFCE2] [PerCS3]GPIO43[NFCE3][DMAReq1][IRQ10] [PerCS4]GPIO44[DMAAck1][IRQ11] [PerCS5]GPIO45[EOT1/TC1][IRQ12] AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group B32 C31 D30 A32 E29 C30 B31 A30 A31 D29 C29 A29 D28 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 21 of 26) Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 ...
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... SGMII0RxClk SGMII0RxClk SGMII0RxD SGMII0RxD SGMII0TxD SGMII0TxD SGMII1RxClk SGMII1RxClk SGMII1RxD SGMII1RxD SGMII1TxD SGMII1TxD SGMIITxClk SGMIITxClk AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group C17 External Peripheral C23 A23 External Peripheral D22 C22 AP30 DDR2/1 SDRAM A17 E17 AL13 AM13 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 23 of 26) Signal Name SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SPAGND SPAV DD SPIClkOut[IIC1SClk] SPIDI SPIDO[IIC1SData] SysClk SysErr SysReset TCK TDI TDO TestEn ...
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... UART0Rx UART0Tx [UART1CTS][UART0DCD]GPIO34[UART2Tx] [UART1RTS][UART0DSR]GPIO35[UART2Rx] [UART1Rx][UART0RI]GPIO39[IRQ6] [UART1Tx][UART0DTR]GPIO38[IRQ5] [UART2Rx][UART0DSR]GPIO35[UART1RTS] [UART2Tx][UART0DCD]GPIO34[UART1CTS] [UART3Rx][UART0CTS]GPIO36[DMAAck3] [UART3Tx][UART0RTS]GPIO37[EOT3/TC3] AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group M29 L30 L31 Trace K33 L32 K34 L33 N29 M31 ...
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... PPC460EX Embedded Processor Table 3. Signals Listed Alphabetically (Part 25 of 26) Signal Name USB2DClk [USB2DD0]GPIO08 [USB2DD1]GPIO09 [USB2DD2]GPIO10 [USB2DD3]GPIO11 [USB2DD4]GPIO12 [USB2DD5]GPIO13 [USB2DD6]GPIO14 [USB2DD7]GPIO15 [USB2DDir]GPIO21 [USB2DNext]GPIO20 [USB2DStop]GPIO19 USB2HClk USB2HClk48 [USB2HD0]GPIO00 [USB2HD1]GPIO01 [USB2HD2]GPIO02 [USB2HD3]GPIO03 [USB2HD4]GPIO04 [USB2HD5]GPIO05 [USB2HD6]GPIO06 [USB2HD7]GPIO07 [USB2HDir]GPIO18 [USB2HNext]GPIO17 [USB2HStop]GPIO16 46 Revision 1.12 – July 17, 2008 ...
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... AMCC Proprietary 460EX – PPC460EX Embedded Processor Ball Interface Group F14 F15 F17 F18 F20 F21 P17 P18 P29 R17 R18 R29 U14 Power U15 U20 U21 U29 V14 V15 ...
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... PPC460EX Embedded Processor Signals in Ball Assignment Order In the following table, only the default signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what other signals or functions can be paragoned to those balls, look up the default signal name in Table 3 on page 22. ...
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... B29 A30 PerAddr12 B30 A31 PerAddr13 B31 A32 PerAddr08 B32 A33 GND B33 A34 GND B34 AMCC Proprietary 460EX – PPC460EX Embedded Processor Signal Name Ball Signal Name GND C01 GND GND C02 GND GND C03 GND PCI0AD19 C04 PCI0IRdy OV C05 ...
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... PPC460EX Embedded Processor Table 4. Signals Listed by Ball Assignment (Part Ball Signal Name Ball E01 PCI0AD24 F01 E02 OV F02 DD E03 PCI0AD22 F03 E04 PCI0AD25 F04 E05 GND F05 E06 PCI0Frame F06 E07 PCI0SErr F07 E08 OV F08 DD E09 PCI0M66En F09 ...
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... K29 J30 GND K30 J31 IIC0SClk K31 J32 GND K32 J33 OV K33 DD J34 GPIO50 * K34 AMCC Proprietary 460EX – PPC460EX Embedded Processor Signal Name Ball Signal Name PCI0Clk L01 AGND GND L02 AGND PCI0Reset L03 AV DD PCI0Req2 L04 PCIE1Rx0 GND L05 ...
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... PPC460EX Embedded Processor Table 4. Signals Listed by Ball Assignment (Part Ball Signal Name Ball N01 PCIE1Tx1 P01 N02 PCIE1Tx1 P02 N03 AV P03 DD N04 PCIE1Rx1 P04 N05 PCIE1Rx1 P05 N06 AV P06 DD N07 No Ball P07 N08 No Ball P08 N09 No Ball P09 ...
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... V V29 DD U30 DM1 V30 U31 DQS1 V31 U32 DQS1 V32 U33 MemData14 V33 U34 MemData15 V34 AMCC Proprietary 460EX – PPC460EX Embedded Processor Signal Name Ball Signal Name PCIE1Tx3 W01 PCIE0Tx0 PCIE1Tx3 W02 PCIE0Tx0 AV W03 PCIE1Rx3 W04 PCIE0RX0 PCIE1Rx3 W05 ...
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... PPC460EX Embedded Processor Table 4. Signals Listed by Ball Assignment (Part Ball Signal Name Ball AA01 PCIE0AVReg AB01 AA02 PCIE0RefClk AB02 AA03 PCIE0RefClk AB03 AA04 AGND AB04 AA05 PAV AB05 DD AA06 V AB06 DD AA07 No Ball AB07 AA08 No Ball AB08 AA09 No Ball ...
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... AF29 AE30 GND AF30 AE31 ClkEn3 AF31 AE32 ECC2 AF32 AE33 ClkEn2 AF33 AE34 ECC3 AF34 AMCC Proprietary 460EX – PPC460EX Embedded Processor Signal Name Ball Signal Name GPIO03 * AG01 GPIO00 * E1OV AG02 GPIO17 * DD GPIO19 * AG03 GPIO20 * GPIO16 * AG04 GPIO18 * GND ...
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... PPC460EX Embedded Processor Table 4. Signals Listed by Ball Assignment (Part Ball Signal Name Ball AJ01 GPIO14 * AK01 AJ02 GPIO11 * AK02 AJ03 GMCMDClk * AK03 AJ04 GPIO12 * AK04 AJ05 GPIO09 * AK05 AJ06 GND AK06 AJ07 No ball AK07 AJ08 GMC0TxER AK08 AJ09 ...
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... AN30 SOV AP30 DD AN31 GND AP31 AN32 BA0 AP32 AN33 GND AP33 AN34 GND AP34 AMCC Proprietary 460EX – PPC460EX Embedded Processor Signal Name Ball Signal Name GND GND GND GND GMC0CD GND GMC0RxD7 GMC0RxD2 GMCRefClk Reserved EAVDD EAGND SGMII1RxD SGMII0RxD ...
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... PPC460EX Embedded Processor Signal Descriptions The PPC460EX embedded controller is packaged in a 728-ball thermally enhanced plastic ball grid array (TE- PBGA). The following tables describe the package level pin-out. Table 5. Pin Summary In the table Table 7 on page 60, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline ...
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... Reserved Pins The balls marked Reserved on this chip are not functional. However, some of the reserved balls cannot be left unconnected. Connect the balls shown in Table 6 as indicated: AMCC Proprietary 460EX – PPC460EX Embedded Processor Table 6. Non-Functional Ball Connections Ball Connection AM15 1kΩ ...
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... PPC460EX Embedded Processor Table 7. Signal Functional Description (Part 1 of 10) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI not used, must pull down (recommended value is 1kΩ ...
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... Note: DC couple only and bias to 0V common mode. Differential transmit signal pairs. PCIE0 is a single-channel (Tx0 only) interface. PCIEnTx0:3 PCIE1 is a four-channel (Tx0:3) interface. PCIEnTx0:3 Lane 0 is LSB. Note: AC couple only. AMCC Proprietary 460EX – PPC460EX Embedded Processor or equivalent. DD Description or equivalent. DD I/O Type Notes 2 ...
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... PPC460EX Embedded Processor Table 7. Signal Functional Description (Part 3 of 10) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI not used, must pull down (recommended value is 1kΩ ...
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... RMII1 1:0: Receive data. GMC0RxD7:4, GMII/MII 0: Receive data. GMC1RxD3:0 RGMII 1: Receive data. GMC0RxDV, GMII/MII 0: Receive data valid. GMC0RxCtl RGMII 0: Receive control. RMII1CrSDV RMII 1: Carrier sense/Receive data valid. AMCC Proprietary 460EX – PPC460EX Embedded Processor or equivalent. DD Description or equivalent. DD I/O Type Notes 3.3V tolerant O 2.5V CMOS 3.3V tolerant I/O 2 ...
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... PPC460EX Embedded Processor Table 7. Signal Functional Description (Part 5 of 10) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI not used, must pull down (recommended value is 1kΩ ...
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... External peripheral device select. Output enable. Used by either peripheral controller or DMA controller depending PerOE upon the type of transfer involved. When the PPC460EX is the bus master, it enables the selected device to drive the bus. PerReady Used by a peripheral slave to indicate it is ready to transfer data. ...
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... PPC460EX Embedded Processor Table 7. Signal Functional Description (Part 7 of 10) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI not used, must pull down (recommended value is 1kΩ ...
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... Data is latched on the rising edge. NFCE0:3 Chip enable. Serial Peripheral Interface SPIClkOut Clock output. SPIDI Data input. SPIDO Data output. Interrupts Interface IRQ0:15 External interrupt requests 0 through 15. AMCC Proprietary 460EX – PPC460EX Embedded Processor or equivalent. DD Description or equivalent. DD I/O Type Notes 3.3V tolerant I/O 2.5V CMOS 3.3V tolerant ...
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... PPC460EX Embedded Processor Table 7. Signal Functional Description (Part 9 of 10) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI not used, must pull down (recommended value is 1kΩ ...
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... SerDes PLL Analog Supply. DD AGND Ground for AV EAV +2.5V—Filtered analog voltage for Ethernet PLLs. DD EAGND Ground for EAV SPAV +2.5V—Filtered analog voltage for system PLL. DD SPAGND Ground for SPAV AMCC Proprietary 460EX – PPC460EX Embedded Processor or equivalent. DD Description and PAV . equivalent. DD I/O ...
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... Case temperature under bias Notes: 1. The analog voltages (AV , EAV , SPAV DD DD must be filtered before entering the PPC460EX. A separate filter for each analog voltage, as shown below, is recommended AGND 2. This value is not a specification of the operational temperature range stress rating only. ...
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... Output Logic High (1.8V SGMII) Output Logic Low 3.3V LVTTL and PCI Output Logic Low 2.5V CMOS Output Logic Low 1.8V DDR2 (2.5V DDR1) Output Logic Low (1.8V SGMII) Input Leakage Current (no pull-up or pull-down) Input Leakage Current for pull-down AMCC Proprietary 460EX – PPC460EX Embedded Processor Symbol Minimum Typical V +1.2 +1. ...
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... C Power Supply Sequencing All the PPC460EX I/O designs are power supply sequence independent. There is no requirement that the power supplies power up in any particular order. The following items are power sequence considerations: • Logic power (V ...
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... Frequency (MHz 600 4.60 800 4.97 1000 5.34 Notes: 1. Typical power is estimated and is based on a nominal voltage of V that exercises each function with representative traffic. AMCC Proprietary 460EX – PPC460EX Embedded Processor Symbol C IN1 C IN2 C IN3 C IN5 C IN6 C IN6 +2.5V Supply +1.8V Supply (E1OV ...
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... PPC460EX Embedded Processor Table 13. V Supply Power Dissipation DD Frequency (MHz) 600 800 1000 Notes: 1. Power is estimated and is based each function with representative traffic. Table 14. DC Power Supply Loads Parameter V (+1.25V) active operating current DD OV (+3.3V) active operating current DD E1OV (+2 ...
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... Thermal Management The following heat sink was used in the above thermal analysis: 35W x 35L x 15H (mm) Base thickness = 1.5mm Fin height = 13.5mm Fin thickness = 1.0mm Number of Fins: 11 aluminum AMCC Proprietary 460EX – PPC460EX Embedded Processor Airflow ft/min (m/sec) Symbol 0 100 200 (0) (0 ...
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... PPC460EX Embedded Processor Thermal Monitor Thermal monitoring of the chip is accomplished using the PNP transistor (β ≈ 2) provided on the chip. The collector of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to chip pins. A voltage measurement (V provides the chip temperature in °K according to the equation: ...
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... Period C Notes: 1. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information” on page 4). Figure 4. Timing Waveform AMCC Proprietary 460EX – PPC460EX Embedded Processor Min 66.66 10 – 40% of nominal period 40% of nominal period 600 ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected. Important the system designer to ensure that any SSCG used with the PPC460EX meets the above requirements and does not adversely affect other aspects of the system. 78 Revision 1.12 – July 17, 2008 ...
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... SGMIIRxClk frequency SGMIIRefClk frequency SMIIRefClk frequency SMIIRefClk accuracy RMIIRefClk frequency RMIIRefClk accuracy RMIIRefClk period RMIIRefClk high time RMIIRefClk low time AMCC Proprietary 460EX – PPC460EX Embedded Processor Minimum Maximum – 66.66 15 – 40% of nominal period 60% of nominal period 40% of nominal period 60% of nominal period – ...
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... PPC460EX Embedded Processor Table 17. Peripheral Interface Clock Timings (Part Parameter PerClk frequency PerClk period PerClk high time PerClk low time SPIClkOut frequency IICSClk frequency TmrClk frequency TmrClk period TmrClk high time TmrClk low time TrcClk frequency UARTSerClk frequency ...
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... Figure 5. Input Setup and Hold Waveform Clock Inputs Figure 6. Output Delay and Float Timing Waveform Clock max min Outputs OH High (Drive) Float (High-Z) Low (Drive) AMCC Proprietary 460EX – PPC460EX Embedded Processor T min T min IS IH Valid max min OH Valid max ...
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... PPC460EX Embedded Processor Figure 7. Input Setup and Hold Timing Waveform for RGMII Signals GMCnRxClk 1.25V Inputs 1.25V RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnRxClk. RGMII 10/100Mb timing is with reference only to the raising edge of GMCnRxClk. Figure 8. Output Delay and Hold Timing Waveform for RGMII Signals GMCnTxClk 1 ...
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... SATA0RefClk na SATA0Rx0 na SATA0Rx0 SATA0Tx0 na SATA0Tx0 Ethernet MII Interface GMCMDIO n/a GMC0TxD3:0 n/a GMC0TxEn n/a GMC0TxEr n/a GMC0CD 10 GMC0CrS 10 GMC0RxD3:0 6 GMC0RxDV 5 GMC0RxEr 6 AMCC Proprietary 460EX – PPC460EX Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min 5 ...
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... PPC460EX Embedded Processor Table 18. I/O Specifications—All Speeds (Part Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. TDO timing is referenced to the falling edge of TCK. Input (ns) Signal Setup Time Hold Time (T min Ethernet GMII Interface GMCMDIO n/a GMC0TxD7:0 ...
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... IRQ0:15 na JTAG Interface TCK n/a TDI 2 TDO n/a TMS 2 TRST n/a System Interface SysReset n/a SysErr n/a Halt n/a TestEn n/a Trace Interface TrcBS0:2 n/a TrcES0:4 n/a TrcTS0:6 n/a AMCC Proprietary 460EX – PPC460EX Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min n/a n/a 0 n/a n/a n n/a n/a 0 ...
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... PPC460EX Embedded Processor Table 19. I/O Specifications—600MHz to 1000MHz Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Signal Setup Time Hold Time (T min External Slave Peripheral Interface DMAReq0:3 4 DMAAck0:3 n/a EOT0:3/TC0:3 ...
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... The paths (traces) for the data and the associated data strobe signal should be routed with the same length between PPC460EX and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the capture logic at the same time the data is in transition. Board designs must meet both of the following criteria: • ...
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... PPC460EX Embedded Processor Figure 9. DDR SDRAM Simulation Signal Termination Model MemClkOut MemClkOut PPC460EX Addr/Ctrl (DDR2) Addr/Ctrl/Data/DQS/DM (DDR1) Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout ...
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... Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ Delay from rising/falling edge of clock to the rising/falling edge of DQS DS Note: The timing data in the following tables is based on simulation runs using Einstimer. AMCC Proprietary 460EX – PPC460EX Embedded Processor Process Speed Junction Temperature (°C) −40 Fast Slow +105 ...
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... PPC460EX Embedded Processor Table 22. I/O Timing—DDR SDRAM T Notes: 1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle. 2. Clock speed is 200MHz. Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 Table 23. I/O Timing—DDR SDRAM T Notes: 1 ...
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... The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS signal. The Data must be centered to these edges for correct operation. The PPC460EX can delay with very fine granularity the DQS through register programming. DDR SDRAM MemClkOut0 and Read Clock Delay In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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... PPC460EX Embedded Processor Figure 11. DDR SDRAM Read Data Path Ext FeedBack Signals Driver MemDCFdbkD Coarse Delay Rec Fine Delay MemDCFdbkR DQS aligned FBK signal Feedback Data Capture Window Package Mux pins FF DQS Rising Edge Sync DQ Data Stage 1 ...
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... It is recommended that the signal length for all of the eight DQS signals be matched. The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the data in Stage 1. AMCC Proprietary 460EX – PPC460EX Embedded Processor and ...
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... PPC460EX Embedded Processor Figure 13. DDR SDRAM Read Cycle Timing—Example DDR 1X Clock DDR 2X Clock Memclk (Diff.) DQS at MemCntl Pin Data at Pin Feedback Output DDR 1X Clock cycle Delayed DQS Data Out Stage 1 (0) Data Out Stage 1 (1) Data out Stage 1 (2) ...
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... During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device connected to the IIC0 port. At the de-assertion of reset, if the Bootstrap Controller is enabled, the PPC460EX sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0:3 registers accordingly. ...
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... PPC460EX Embedded Processor Revision Log Date Version 04/20/2007 1.00 05/17/2007 1.00 07/18/2007 1.01 08/03/2007 1.02 10/01/2007 1.03 10/17/2007 1.04 10/18/2007 1.05 12/21/2007 1.06 01/14/2008 1.07 02/11/2008 1.08 04/14/2008 1.09 05/05/2008 1.10 05/29/2008 1.11 07/17/2008 1.12 96 Contents of Modification Initial creation of document. Update to initial creation of document. Update to initial creation of document. Update to initial creation of document. Eliminate SRIO, EMB, second RGMII, SMII, third and forth EMACs. ...
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... AMCC test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein. AMCC Proprietary 460EX – PPC460EX Embedded Processor 97 ...
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... PPC460EX Embedded Processor 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’ ...