ppc460ex Applied Micro Circuits Corporation (AMCC), ppc460ex Datasheet - Page 10

• Manufacturer Part Number: ppc460ex
• Description: Powerpc 460ex Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

460EX – PPC460EX Embedded Processor
PowerPC 440 Processor
The PowerPC 440 processor (in 90nm technology) is designed for high-end applications: RAID controllers, SAN,
iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture
and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
Floating Point Unit (FPU)
The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers
single cycle through put on most instructions.
Features include:
L2 Cache/SRAM
The PPC460EX also provides a 256KB L2 cache between the Processor Local Bus and the processor’s D- and
I-caches. This memory unit can be alternatively programmed to function as 256KB of SRAM.
Features include:
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• Up to 1GHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• Three execution pipelines
• Dynamic branch prediction
• Memory management unit
• Debug facilities
• 24 DSP instructions
• Five stages with 2 MFlops/MHz
• Hardware support for IEEE 754
• Single- and double-precision
• Single-cycle throughput on most instructions
• Thirty-two 64-bit floating point registers
• Four banks of 64KB each
• Memory cycles supported:
– UTLB Word Wide parity on data and tag address parity with exception force
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
– Single beat read and write, 1 to 16 bytes
– Quadword Read and Write burst for 12-bit master
– Guarded memory accesses on 4KB boundaries
Preliminary Data Sheet
Revision 1.12 – July 17, 2008
AMCC Proprietary