ppc460ex Applied Micro Circuits Corporation (AMCC), ppc460ex Datasheet - Page 13

• Manufacturer Part Number: ppc460ex
• Description: Powerpc 460ex Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

Revision 1.12 – July 17, 2008
PCI Controller
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.3 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
Features include:
PCI Express Controller
There are two independent PCI Express interfaces compliant with PCI Express base specification 1.1. One
interface can be configured as one to four lanes while the other functions as one-lane only. Both can be Root or
Endpoint Ports. The single lane interface shares a High-Speed SERDES with the Serial ATA (SATA) interface.
Features include:
AMCC Proprietary
Preliminary Data Sheet
• PCI Specification Version 2.3
• PCI Bus Power Management Interface Specification Version 1.1
• Frequency to 66MHz
• 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to four external devices, that can be disabled for use with an
• Support for inbound and outbound Message Signaled Interrupts (MSI)
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfers of the following types:
• Vital Product Data (VPD) support
• Two independent PCI Express interfaces
• Compliant with PCI Express base specification 1.1
• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
• Power Management
• Supports one virtual channel (VC0) no Traffic Class (TC) filtering
• Maximum Payload block size 512 Bytes
• Supports up to 512 Bytes maximum Read request size
• Requests supported:
external arbiter
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
– One 4 lanes
– One 1 lane
– 2.5 GB/sec full duplex per lane
– Applications compliant with MSI rules are limited to one Endpoint port per PPC460EX
– up to 4 (x4) or 2 (x1) posted outbound Write requests (memory and messages)
– up to 4 (x4) or 2 (x1) posted inbound Write requests
– up to 4 (x4) or 2 (x1) outbound Read requests outstanding on PCI Express
– up to 4 (x4) or 2 (x1) inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express Endpoint
460EX – PPC460EX Embedded Processor
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