ppc460ex Applied Micro Circuits Corporation (AMCC), ppc460ex Datasheet - Page 14

• Manufacturer Part Number: ppc460ex
• Description: Powerpc 460ex Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

460EX – PPC460EX Embedded Processor
DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-
DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing
modes are programmable. This controller interfaces to the PLB through a Memory Queue (MQ) function that
includes six high-speed 1KB FIFO buffers.
The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5V
and DDR2 devices require +1.8V.
Features include:
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• Buffering in each PCI Express port for the following transaction types:
• Parity checking on each buffer
• Programmable Outbound Memory (POM) regions: 3 memory, 1 I/O, 1 message, 1 configuration, 1 internal
• Programmable Inbound Memory (PIM) regions: 4 memory, 1 I/O, 1 expansion ROM
• INTx Interrupts support (legacy PCI):
• MSI - Message Signaled Interrupts
• Registered and non-registered industry standard DIMMs
• DDR2 333/400 support
• 64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 3.2GB/s peak bandwidth for the 64-bit interface
• 1.6GB/s peak bandwidth for the 32-bit interface
• Four chip (bank) select signals supporting four external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
• Up to 16GB in four external banks
• Up to two MemClkOut signals
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency and High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency and High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two 1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers
register
bank)
– 2KB Replay buffer: up to 4 in flight transactions
– 2KB (x4) or 1KB (x1) for Outbound posted Writes
– 2KB (x4) or 1KB (x1) for Outbound Reads completion
– 2KB (x4) or 1KB (x1) for Inbound posted Writes
– 2KB (x4) or 1KB (x1) for Inbound Reads completion
– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types generation for Endpoints
– MSI generation for Endpoint
– MSI termination for Root Ports
– MSI_X termination for Root Ports
Preliminary Data Sheet
Revision 1.12 – July 17, 2008
AMCC Proprietary