adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 11

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

DMA transfers. Vector interrupt support provides efficient
execution of host commands.
General-Purpose I/O Ports
The SHARC Mel-100 also contains 12 programmable, general-
purpose I/O pins that can function as either inputs or outputs.
As outputs, these pins can signal peripheral devices; as inputs,
these pins can provide the test for conditional branching.
Program Booting
The internal memory of the SHARC Mel-100 can be booted at
system power-up from either an 8-bit EPROM, a host processor,
the SPI interface, or through one of the link ports. Selection of
the boot source is controlled by the Boot Memory Select ( BMS ),
EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.
8-, 16-, or 32-bit host processors can also be used for booting.
Phased-Locked Loop and Crystal Double Enable
The SHARC Mel-100 uses an on-chip phase-locked loop (PLL)
to generate the internal clock for the core. The CLK_CFG[1:0]
pins are used to select ratios of 2:1, 3:1, and 4:1. In addition to
the PLL ratios, the CLKDBL pin can be used for more clock
ratio options. The (1×/2× CLKIN) rate set by the CLKDBL pin
determines the rate of the PLL input clock and the rate at which
the synchronous external port operates. With the combination
of CLK_CFG[1:0] and CLKDBL , ratios of 2:1, 3:1, 4:1, 6:1, and
8:1 between the core and CLKIN are supported. See Figure 13.
Power Supplies
The SHARC Mel-100 has separate power supply connections
for the internal (V
(AV
must meet the 1.8 V requirement. The external supply must
meet the 3.3 V requirement. All external supply pins must be
connected to the same supply.
Note that the analog supply (AV
processor’s clock generator PLL. To produce a stable clock,
provide an external circuit to filter the power input to the AV
pin. Place the filter as close as possible to the pin. For an
example circuit, see Figure 7. To prevent noise coupling, use a
wide trace for the analog ground (AGND) signal and install a
decoupling capacitor as close as possible to the pin.
DD
/AGND) power supplies. The internal and analog supplies
DDINT
), external (V
DD
) powers the SHARC Mel-100
DDEXT
), and analog
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DD
CLOCK
V
DDINT
RESET
Figure 8. Shared Memory Multiprocessing System
3
2
1
Figure 7. Analog Power (AV
CLKIN
ID2
ID2
CLKIN
ID2
RESET
CLKIN
RESET
RESET
ADSP-21161 #4
ADSP-21161 #3
ADSP-21161 #2
ADSP-21161 #1
10Ω
–
–
–
0
0
0
SDCLK[1
DATA47
DATA47
DATA47
ADDR23
CONTROL
ADDR23
CONTROL
ADDR23
0.1µF
SDCKE
SDA10
MS3
BR6
ADSST-SHARC-Mel-100
SDWE
REDY
SBTS
BMS
HBG
DQM
ACK
HBR
RAS
CAS
BR1
–
–
–
WR
RD
CS
–
16
–
16
–
16
–
–
–
0]
0
0
0
0
2
AGND
DD
) Filter Circuit
0.01µF
ADDR
DATA
CS
ADDR
DATA
OE
WE
ACK
CS
ADDR
DATA
RAS
CAS
DQM
WE
CLK
CKE
A10
CS
ADDR
DATA
PERIPHERALS
(OPTIONAL)
PROCESSOR
INTERFACE
(OPTIONAL)
MEMORY
(OPTIONAL)
(OPTIONAL)
GLOBAL
AV
EPROM
AND
SDRAM
HOST
BOOT
DD