adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 6

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

ADSST-SHARC-Mel-100
With its SIM
the SHARC Mel-100 can perform 600 million math operations
per second. Table 1 shows performance benchmarks for the
SHARC Mel-100.
The SHARC Mel-1
standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features. These features include a 1-Mbit dual-ported SRAM
memory, a host processor interface, an I/O processor that
supports 14 DMA channels, four serial ports, two link ports, a
SDRAM controller, an SPI interface, an external parallel bus,
and glueless multiprocessing.
Figure 2 illustrates the followin
• Two processing elements, each made up of an AL
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cach
• PM and DM buses capable of supporting fo
•
• On-chip SRAM
• SDRAM controller for gluel
• External port that supports
• D
• Four serial ports
• Two link ports
• SPI compatible
• JTAG test access port
• 12 general-purpose I/O
Figure 4 shows a typical single-p
multiprocessing system appears in Figure 8.
multiplier, shifter, and data register file
data transfers between memory and the core every co
processor cycle
Interval timer
MA controller
• Interfacing to off-chip me
• Glueless multiprocessing for six SHARC Mel-1
• Host port read/write of IOP registers
processors
D computational hardware running at 100 MHz,
00 continues the SHARC’s industry-leading
interface
(0.5 Mbit)
g architectural features:
pins
ess interface to SDRAMs
rocessor system. A
mory peripherals
e
ur 32-bit
U,
00
re
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n
SHARC MEL-100 FAMILY CORE ARCHITECTURE
The SHARC Mel-100 includes the following architectural
features of the ADSP-2116x family core:
SIMD Computational Engine
The SHARC Mel-100 contains two computational processing
elements that operate as a Single Instruction Multiple Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY, and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both
processing elements, but each processing element operates on
different data. This architecture is efficient at executing math-
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required to
sustain computational operation in the processing elements.
Because of this requirement, entering SIMD mode also doubles
the bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the
register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point, and
32-bit fixed-point data formats.
Table 1. Benchmarks (at 100 MHz)
Benchmark Algorithm
1024 Point Complex FFT
(Radix 4, with Reversal)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply (Pipelined)
Divide (y/x)
Inverse Square Root
DMA Transfers
1
Assumes two filters in multichannel SIMD mode
[3 × 3] • [3 × 1]
[4 × 4] • [4 × 1]
1
1
1
Speed (at 100 MHz)
171 µs
5 ns
40 ns
30 ns
37 ns
60 ns
40 ns
800 Mbytes/s