adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 4

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

ADSST-SHARC-Mel-100
GENERAL DESCRIPTION
The SHARC Mel-100 family of powerful 32-bit audio
processors from Analog Devices enables flexible designs and
delivers a host of features across high-end and high fidelity
audio systems to the AV receiver and DVD markets. It includes
multichannel audio decoders, encoders, and postprocessors for
digital audio designs using DSPs in home theater systems and
automotive audio receivers.
With 32-bit audio quality, the SHARC Mel-100 audio processor
autodetects and decodes audio formats in real time, enabling
end users to enjoy a theater-quality audio experience in their
homes and automobiles.
The designs can be customized to meet the exact requirements
of the application. This audio DSP system enables designers to
make value additions to product features working off the high-
end base functionality with which they are provided.
Evaluation boards, sample applications, and all necessary
software support (e.g., drivers) are available. The evaluation
board enables OEMs to offer comprehensive and single-chip
implementations of advanced features for end-user products.
SHARC Mel-100 audio processors enable OEMs to produce
high quality, low cost designs featuring decoder algorithms and
postprocessors for DTS-ES Extended Surround (including both
DTS Discrete 6.1 and DTS Matrix 6.1), DTS Neo:6, Dolby
Digital, Dolby Pro Logic II, AAC, and WaveSurround.
The cost of development is reduced, enabling common
solutions across product lines. Field and remotely upgradeable
products with programmable DSPs and an optimized library of
routines, along with the best development tools in the industry,
reduce the time to market.
SHARC Mel-100 is the comprehensive answer to the needs of
the high-end, high quality digital audio market. It delivers a
realistic high fidelity audio experience along with the maximum
number of features in the product, across price points in the
high-end home theater and DVD markets.
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HARDWARE ARCHITECTURE
Hardware architecture includes the interface between the DSP
and the host microcontroller, command processing, data
transfer in serial and parallel form, data buffer management,
algorithm combinations, MIPS, and memory requirements that
are provided.
The multichannel algorithms are implemented on a SHARC
Mel-100 AVR evaluation board. The board is standalone and
accepts a compressed digital bit stream as serial input from
LD/DVD/CD players or stream generators, decodes the bit
stream, and generates a PCM stream in real time in
2-channel or multichannel mode. It has a microcontroller to
handle commands and option selections from a small keypad
and an LCD display for status display.
To understand the SHARC Mel-100 family hardware
architecture, one should examine its four major blocks:
The hardware architecture of the SHARC Mel-100 is complex. It
has four independent buses for dual data, one for instructions,
and one for I/O fetch. Since the four buses are independent,
multiple transactions take place within a single clock cycle. It
has two external ports, DMA channels, and eight serial ports. It
is a 0.35 ns technology IC operating at 3.3 V.
TRANSMITTER
• The Core Processor
• Dual-Ported SRAM
• External Port
• Input/Output Processor
RECEIVER
S/PDIF
S/PDIF
ADC
DAC
BOOT ROM
128k × 32,
SDRAM
1M × 8
Figure 2. Simplified Block Diagram
SERIAL PORT
GPIO
IRQ
CHANNEL
CODEC
MULTI-
HOST MICRO
KERNEL
COMMAND