ia3513 integration, ia3513 Datasheet - Page 22

• Manufacturer Part Number: ia3513
• Description: Headset Voice And Power Solution
• Manufacturer: integration

Current address read
The address register keeps track of the last register accessed. A simple I2C read cycle always reads the last accessed register
(either trough a read or through a write), as long as power is maintained, and a system reset isn’t issued.
Timing Diagrams
Symbol
t
t
t
t
t
t
t
HD.STA
HD.DAT
SU.DAT
SU.STO
DO.VAL
DO.HLD
SU.STA
t
t
t
f
HIGH
LOW
SCL
BUF
t
t
R
F
SDA
SCL
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
Rise Time
Fall Time
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Stop Condition Setup Time
Data Output Valid (from clock low)
Data Output Hold Time (from clock low)
Time the bus must be free between transfers
START
t
HD.STA
t
SAD[6:0]
AD[7:0]
HD.DAT
D[7:0]
Field
t
D
HIGH
IN
t
LOW
Width
(bits)
D
Timing Diagram for a Random Write
t
7
8
8
SU.DAT
IN
Bus Timing Diagram
Description
Slave address
Register address
Register data
t
SU.STA
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
20
20
45
45
0
START
t
DO.VAL
Typ
t
F
t
DO.HLD
D
OUT
t
R
Max
400
300
300
245
245
0.9
STOP
t
SU.STO
START
Unit
kHz
µ s
µ s
ns
ns
us
us
us
ns
us
ns
ns
us
t
IA3513
BUF
22