uaa1570hl NXP Semiconductors, uaa1570hl Datasheet - Page 36

• Manufacturer Part Number: uaa1570hl
• Description: Global Positioning System Gps Front-end Receiver Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The SCLK input of the UAA1570HL is self-biased at 50%
of the analog supply voltage (V
threshold level. It is therefore possible to operate this input
with levels as low as 10 mV (peak value) in order to avoid
large digital signal flow on the Printed-Circuit Board (PCB)
runners. This is done in the default application with a
6.8 and 3.9 k resistive divider followed by a 10 pF AC
coupling series capacitor in between the SAA1575HL and
the UAA1570HL.
However, when it is nevertheless intended to use full
CMOS or TTL levels, some attenuation is required so that
the peak sample clock input does not exceed 75% of the
UAA1570HL analog supply voltage. This is especially
important while the UAA1570HL is operating from a lower
supply (3 V) than the SAA1575HL (5 V). A resistive divider
can help in these cases, but the AC coupling method
described above should be preferred.
7.8.2
The UAA1570HL internal sample clock squaring circuit
allows single-ended sinusoidal clock inputs as low as
10 mV (peak value) over a frequency range from
5 to 35 MHz. The rise time of the clock output should be in
the order of 25% of the maximum sampling frequency to
ensure that aperture losses are less than approximately
1 dB (0.91 dB). The period of a 35 MHz clock is 28.57 ns.
To keep the sampling aperture on the order of one fourth
this period implies a rise time of 5.7 ns
required and should also be kept with lower sampling clock
rates.
Using a 14.4 MHz sampling rate test signal into the SCLK
input results in good TTL eye pattern characteristics over
a measured input range down to at least 25 dBm.
At 35 dBm the effects of slew rate limiting begin to appear
Two clocked D flip-flops are connected in a master/slave
configuration to implement the sampling function of the
1-bit sampler. With the internal DFF clock (CLK) LOW the
master flip-flop DFF1 is in its transparent mode and
continuously follows the amplitude quantized limiter
output. As the clock (CLK) goes HIGH the data is latched
in the master flip-flop and the slave DFF2 becomes
transparent to the latched output from the master flip-flop.
The falling edge of the CLK signal latches the slave and
again loads the limiter output into the master flip-flop.
These stages also provide additional limiting gain for
marginal input signals from the limiter.
1999 May 10
with the eye pattern closing beyond 40 dBm.
7.8.3
Global Positioning System (GPS) front-end
receiver circuit
CMOS
T
IME QUANTIZATION
TO
ECL
SAMPLE CLOCK SQUARING CIRCUIT
(
SAMPLER
CCA
) near the internal
)
28.57 ns
---------------------- -
4 1.25
is
36
Since the TTL/CMOS output stage is transparent the SIGN
bit output is updated on the rising edge of the CLK with the
master latched and the slave transparent. This implies the
DSP can expect SIGN bit data to be latched on the LOW
CLK state.
7.8.4
The TTL output stage is a variation of a totem pole
modified to operate from an independent isolated supply
voltage from 2.7 to 5.5 V. This supply voltage is also
independent of other supply voltages used in the
UAA1570HL. Circuits to minimize cross-conductance and
short-circuit currents are provided.
Operating from a 2.7 V supply, V
132 mV and 1.95 V, respectively. Operating from a 5.5 V
supply, V
respectively.
Typical rise times of 8 ns and fall times of 10 ns can be
expected from this output driving CMOS loads.
7.8.5
The rise and fall times of the TTL output with a 15 pF load
are approximately 8 ns and are relatively independent of
supply and temperature. A small decrease (1 to 2 ns) in
rise and fall times is seen at T
increase at T
Typical propagation delay times through the time
quantization circuitry while switching amplitude
quantization states from a 5.5 V supply are:
7.9
The UAA1570HL includes a programmable synthesizer
allowing the main, second LO and reference dividers to be
programmed under external control via a three-wire serial
control bus. Alternatively, a LOW on the STROBE input on
power-up will load a 20-bit default frequency plan word and
power-on options into the synthesizer registers.
Frequency plans with a 2nd IF of
4
7.9.1
After the VCO signal leaves its single-ended-to-balanced
cascode buffer it is again amplified on its way to a high
speed fixed divide-by-2 prescaler using a super buffer
such as that described for the first mixer (see Section 7.3).
SCLK input to TTL SIGN output 16 ns (rising edge)
SCLK input to TTL SIGN output 17.6 ns (falling edge).
f
0
(1.023 MHz) = 4.092 MHz can be implemented.
Programmable synthesizer
TTL
1-
VCO
OL
BIT DELAYS
and V
amb
OUTPUT STAGE
PRESCALER
= 120 C (2 to 4 ns).
OH
are nominally 195 mV and 4.6 V,
amb
OL
= 55 C and a small
and V
UAA1570HL
Product specification
OH
are nominally