uaa1570hl NXP Semiconductors, uaa1570hl Datasheet - Page 38

• Manufacturer Part Number: uaa1570hl
• Description: Global Positioning System Gps Front-end Receiver Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
This ratio can again be optionally doubled by setting n7
LOW. The range is then extended to values from
256 to 508, inclusive, in increments of 4. Equal
mark/space-ratio signals are always fed to the main
synthesizer port of the phase frequency detector since the
fixed divide-by-2 post scaler is always present. The main
synthesizer path divisions ratio range, including the fixed
divide-by-2 and divide-by-3 prescalers, is increased by a
factor of 6 from 768 to 1524 in increments of 12 when
n7 is set HIGH or from 1536 to 3048 in increments of 24
if n7 is set LOW. The total default main synthesizer path
division ratio from the VCO is 12
(n0, n1, n2, n3, n4, n5, n6, n7 = 1, 1, 1, 0, 0, 0, 1, 1).
7.10.6
The last four bits clocked into the DATA register set the
programmable division ratio for the 2nd local oscillator.
Again the MSB is read in first with the binary word set to a
number between 4 and 15.
The default values are set to 10 (l0, l1, l2, l3 = 0, 1, 0, 1).
Again a post scaler is provided with a fixed divide-by-2
value to ensure that the LO signal exhibits equal
mark/space ratios driving the second mixer.
The programmable divider and fixed post scaler provide
division between 8 and 30 in even increments. Since the
2nd local oscillator path from the VCO includes the
divide-by-2 prescaler common to both the L-divider and
N-divider paths, the total programmable 2nd local
oscillator division range, relative to the VCO, is 16 to 60 in
increments of 4.
With the 20-bit programming word completely clocked into
the DATA register the STROBE signal is returned to a
HIGH state after a minimum delay of 30 ns to latch and
effect the parallel loading of the programmed word states.
7.11
The complete default program word once serially loaded
or loaded by default on power-up with the STROBE held
LOW realizes the following frequency plan in the
UAA1570HL. It should be noted that the MSB for the
complete 20-bit program word is l0 and the Least
Significant Bit (LSB) is p1 with the latter the first loaded into
the DATA register. This is in contrast to the sequence in
which the different bits determining the individual divider
ratios are structured. The resulting default 20-bit word is:
l0, l1, l2, l3, n0, n1, n2, n3, n4, n5, n6, n7, r0, r1, r2, r3,
r4, r5, p0, p1 =
0, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0.
1999 May 10
Global Positioning System (GPS) front-end
receiver circuit
The serial interface word
l0, l1, l2
AND
l3
71 or 852 with
38
7.12
The default synthesizer programming produces the
following frequency plan:
Table 2 Frequency plan
7.13
The phase detector is of a phase and frequency sensitive
digital type. In conjunction with the charge pump, it
operates without a ‘dead zone’.
The charge pump itself has a single-ended output
delivering or sinking current pulses with a maximum
amplitude of 240 A into the external loop filter.
The layout for the connection between the loop filter and
the VCO input should be made with utmost care in order to
avoid other signals entering this path.
The loop filter as chosen on the demonstration board
yields a loop bandwidth of approximately 100 kHz, with a
damping constant of 1. It consists of a 3.9 nF capacitor
and a series resistor of 20 k , both in parallel with a
150 pF capacitor.
RF input frequency
VCO frequency
RF image frequency
First IF frequency
Second LO division ratio
Second LO frequency
Second image frequency
Second IF frequency
Reference frequency
Total main synthesizer division
ratio
Total reference division ratio
Phase comparison frequency
The default frequency plan
Phase detector, charge pump and loop filter
PARAMETER
UAA1570HL
1.57542 GHz
1.5336 GHz
1.49178 GHz
41.82 MHz
2
38.34 MHz
34.86 Hz
3.48 MHz
14.4 MHz
2
2
1.8 MHz
Product specification
10
3
4 = 8
VALUE
71
2 = 40
2 = 852