m28f010 Intel Corporation, m28f010 Datasheet - Page 4

• Manufacturer Part Number: m28f010
• Description: 1024k 128k X 8 Cmos Flash Memory
• Manufacturer: Intel Corporation

M28F010
NOTES
1 V
programming voltage specified for the device Refer to DC Characteristics When V
read but not written or erased
2 Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 3 All other
addresses low
3 Read operations with V
4 With V
5 Refer to Table 3 for valid Data-In during a write operation
6 X can be V
7 V
Or the system designer may choose to ‘‘hardwire’’
V
available In this instance all operations are per-
formed in conjunction with the command register
The M28F010 is designed to accommodate either
design practice and to encourage optimization of
the processor-memory interface
Integrated Stop Timer
Sucessive command write cycles define the dura-
tions of program and erase operations specifically
the program or erase time durations are normally
terminated by associated program or erase verify
commands An integrated stop timer provides simpli-
fied timing control over these operations thus elimi-
nating the need for maximum program erase timing
specifications Programming and erase pulse dura-
tions are minimums only When the stop timer termi-
nates a program or erase operation the device
enters an inactive state and remains inactive until
receiving the appropriate verify or reset command
Write Protection
The command register is only active when V
high voltage Depending upon the application the
system designer may choose to make the V
4
READ WRITE
PP
READ-ONLY
PPL
ID
is the intelligent Identifier high voltage Refer to DC Characteristics
making the high voltage supply constantly
may be ground a no-connect with a resistor tied to ground or as defined in the Characteristics Section V
PP
at high voltage the standby current equals I
IL
or V
IH
Operation
Read
Output Disable
Standby
intelligent Identifier (Mfr)
intelligent Identifier (Device)
Read
Output Disable
Standby
Write
PP
e
(4)
V
PPH
may access array data or the intelligent Identifier codes
Table 2 M28F010 Bus Operations
(2)
PP
Pins
PP
(2)
pow-
is at
CC
V
V
V
V
V
V
V
V
V
V
a
PP (1)
PPH
PPH
PPH
PPH
PPL
PPL
PPL
PPL
PPL
I
PP
er supply switchable available only when memory
updates are desired When V
tents of the register default to the read command
making the 28F010 a read-only memory In this
mode the memory contents cannot be altered
Or the system designer may choose to ‘‘hardwire’’
V
available In this case all Command Register func-
tions are inhibited whenever V
lockout voltage V
tion) The 28F010 is designed to accommodate ei-
ther design practice and to encourage optimization
of the processor-memory interface
BUS OPERATIONS
Read
The M28F010 has two control functions both of
which must be logically active to obtain data at the
outputs Chip-Enable (CE) is the power control and
should be used for device selection Output-Enable
(OE) is the output control and should be used
to gate data from the output pins independent of
device selection Figure 6 illustrates read timing
waveforms
PP
(standby)
V
V
A
A
A
A
X
X
X
X
IH
IL
0
0
0
0
making the high voltage supply constantly
V
V
A
A
ID (7)
ID (7)
A
A
X
X
X
X
9
9
9
9
LKO
PP
V
V
CE
V
V
V
V
V
V
V
IH
IH
IL
IL
IL
IL
IL
IL
IL
e
(See Power Up Down Protec-
V
OE
V
V
V
V
V
V
V
PPL
X
X
IH
IH
IH
IL
IL
IL
IL
memory contents can be
PP
CC
WE
V
V
V
V
V
V
V
X
X
IH
IH
IH
IH
IH
IH
IL
e
is below the write
V
Data Out
Tri-State
Tri-State
Data
Data
Data Out
Tri-State
Tri-State
Data In
PPL
DQ
0
PPH
e
e
the con-
– DQ
(5)
89H
B4H
(3)
is the
7