m28f010 Intel Corporation, m28f010 Datasheet - Page 6

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m28f010

Manufacturer Part Number
m28f010
Description
1024k 128k X 8 Cmos Flash Memory
Manufacturer
Intel Corporation
Datasheet

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M28F010
COMMAND DEFINITIONS
When low voltage is applied to the V
tents of the command register default to 00H en-
abling read-only operations
NOTES
1 Bus operations are defined in Table 2
2 IA
3 ID
4 Following the Read int e ligent ID command two read operations access manufacturer and device codes
5 Figure 5 illustrates the Quick-Erase Algorithm
6 Figure 4 illustrates the Quick-Pulse Programming Algorithm
7 The second bus cycle must be followed by the desired command register write
6
Read Memory
Read intelligent Identifier Codes
Set-up Erase Erase
Erase Verify
Set-up Program Program
Program Verify
Reset
EA
PA
Addresses are latched on the falling edge of the Write-Enable pulse
EVD
PD
PVD
e
e
e
e
e
(7)
e
e
Identifier address 00H for manufacturer code 01H for device code
Data read from location IA during device identification (Mfr
Address of memory location to be read during erase verify
Address of memory location to be programmed
Data to be programmed at location PA Data is latched on the rising edge of Write-Enable
Data read from location PA during program verify PA is latched on the Program command
Data read from location EA during erase verify
Command
(5)
(6)
(5)
(6)
(4)
Cycles
Req’d Operation
Bus
PP
1
2
2
2
2
2
2
Table 3 Command Definitions
pin the con-
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
(1)
Address
Placing high voltage on the V
write operations Device operations are selected by
writing specific data patterns into the command reg-
ister Table 3 defines these M28F010 register
commands
e
EA
X
X
X
X
X
X
89H Device
(2)
Data
00H
90H
20H
A0H
40H
C0H
FFH
(3)
e
Operation
B4H)
Read
Write
Read
Write
Read
Write
Second Bus Cycle
(1)
PP
Address
pin enables read
PA
IA
X
X
X
X
(2)
Data
EVD
PVD
FFH
20H
PD
ID
(3)

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